UCC29910A_15 Datasheet, PDF (6/23 Pages) Texas Instruments – Buck PFC Controller

UCC29910A
SLUSAK8A – MAY 2011 – REVISED JUNE 2011
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Pin 8 – FAULT: This pin when pulled low causes PFCDRV and BIASCTRL to go low, typically within 10 us. After
a 100 us delay the FAULT input is sampled again. If the FAULT has cleared high, the UCC29910A goes into
SmartStart mode. If the FAULT input is still low the device enters a latched shutdown state.
Pin 9 – BIASSNS: This pin is used to sense the PFC stage bias rail (normally in the 8 V to 12 V range to drive
the PFC power MOSFET) during start-up to allow control of the external start-up FET. The voltage at this pin
must be greater than V_B(max) before PFCDRV switching commences. If the voltage drops below V_B(min) the
BIASCTRL output goes low, which can enable an external start-up FET.
Pin 10 – TST: This pin provides no user function. It must be connected to VDD.
Pin 11 – NC: This pin is for internal use only, and must be normally left open.
Pin 12 – BIASCTRL: This pin allows control of an external start-up FET.
Pin 13 – PFCDRV: This pin is used to drive the low-side PFC FET indirectly. This pin should be connected to a
level-shifting gate driver to provide the required drive signal amplitude for typical high voltage power FETs. For
this drive signal, D_MAX is limited to 90% duty cycle.
Pin 14 – VSS: This pin is the common ground connection for the device.
UCC29910A Functional Block Diagram
VDD ¹
+
1.92 V
POR
UCC29910A
EN
“Smart-Start”
Soft Start
Burst Control
Start- up Burst
LINESNS ₄
Brown- out _{Run/ Stop}
Detection & Filter
Latch reset detect
Gate Control
Logic
14 VSS
13 PFCDRV
VBULK 2
CS 3
CS 5
BULK OV
Clamp
PFCDRV Blanking
REF
Voltage Loop
PI Error Amp
+
-
EN
PFC Duty Cycle
PWM
Generator
Light Load Detect
Burst Mode
Control
CLK
Oscillator
Disable
EN
Fault Latch
EN
8 ^FAULT
9 BIASSNS
REFIN 6
NC 7
REF
11
NC
Startup
EN
Bias Control
12 _BIASCTRL
10 _TST
UDG-11105
6
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