UCC29910A_15 Datasheet, PDF (2/23 Pages) Texas Instruments – Buck PFC Controller

UCC29910A
SLUSAK8A – MAY 2011 – REVISED JUNE 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PART NUMBER
UCC29910APW
UCC29910APWR
ORDERING INFORMATION
PACKAGE
Plastic, 14-Pin TSSOP (PW)
Plastic, 14-Pin TSSOP (PW)
PACKING
90-Pc. Tube
2000-Pc. Tape and Reel
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) ^(1)(2)(3)
V_DD Supply Voltage
T_A
T_J
T_STG
Voltage: All pins
Operating free air temperature, ⁽⁴⁾
Operational junction temperature, ⁽⁴⁾
Storage temperature ⁽⁴⁾
Lead temperature (10 seconds)
VALUE
4.1
-0.3
−0.3 to VDD + 0.3
−40 to 105
−40 to 105
260
UNIT
V
°C
(1) These are stress limits. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at
these or any conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to
absolute maximum rated conditions for extended periods of time may affect device reliability.
(2) All voltages are with respect to VSS.
(3) All currents are positive into the terminal, negative out of the terminal.
(4) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak
reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
THERMAL INFORMATION
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
PINS
UNITS
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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