TNETE2004 Datasheet, PDF (6/46 Pages) Texas Instruments – MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

TNETE2004
MDIO-MANAGED QuadPHY
FOUR 10BASE-T PHYSICAL-LAYER INTERFACES
SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997
Terminal Functions
controller interface
TERMINAL
NAME
NO.
I/O†
120 128
DESCRIPTION
AUTONEG
74
82
Auto-negotiation. When high, AUTONEG enables auto-negotiation on all four PHYs.
I
Auto-negotiation takes place only after a reset or when a link is reestablished. AUTONEG can be
overridden from the MDI.
COL0
COL1
COL2
COL3
117 127
34
40
56
62
93 103
O
Collision sense. When asserted, COL0–COL3 indicates that PHY0–PHY3 sensed a network
collision. The active level is set by the compatibility pins (see Table 2) or by setting the correct bits
in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13.
CRS0
CRS1
CRS2
CRS3
2
4
29
35
61
67
88
98
Carrier sense. When asserted, CRS0–CRS3 indicates that PHY0–PHY3 is receiving a frame
O
carrier signal. The active level is set by the compatibility pins (see Table 2) or by setting the correct
bits in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13.
DUPLEX0
DUPLEX1
DUPLEX2
DUPLEX3
Duplex mode. When DUPLEX0–DUPLEX3 is high, PHY0–PHY3 operates in full-duplex mode.
When DUPLEX0–DUPLEX3 is low, PHY0–PHY3 operates in the half-duplex mode. There is an
5
7
internal weak drive on DUPLEX0–DUPLEX3 that pulls DUPLEX0–DUPLEX3 if auto-negotiation
26
64
32
70
O/D
chooses the full-duplex mode, or if full duplex is chosen by writing to an MDI register. By connecting
DUPLEX0–DUPLEX3 GND or VDD, this weak drive is overridden, and the type of duplex mode is
85
95
permanently set, ignoring any auto-negotiation decisions or values written to the appropriate MDI
registers. To set duplex mode, connect the auto-negotiation pin low. (This turns off
auto-negotiation.)
LINK0
LINK1
LINK2
LINK3
4
6
27
33
63
69
86
96
Link status. When LINK0–LINK3 is high, it indicates that PHY0–PHY3 has determined that a valid
O
10BASE-T link has been established. When low, LINK0–LINK3 indicates that the link has not been
established.
LOOPBACK 16
20
Loopback. When low, LOOPBACK enables internal loopback in all four PHYs. When asserted, data
I
is internally wrapped within each PHY and does not appear on the network. While in the
looped-back state, all network lines are placed in a noncontentious state. LOOPBACK can be
overridden by the MDI registers.
RXCLK0
RXCLK1
RXCLK2
RXCLK3
1
3
31
37
59
65
89
99
Receive clock. Receive clock source for the receive data output RXD0–RXD3. Data is valid on
O
RXD0–RXD3 on the edges of RXCLK0–RXCLK3 specified by the currently set compatibility mode
(see Table 2) or by setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are
described in Table 13.
RXD0
RXD1
RXD2
RXD3
3
5
28
34
62
68
87
97
O
Receive data. Bit-wise serial-data output from PHY0–PHY3.
SQE
75
83
Signal quality error. When high, SQE causes each PHY to simulate a collision condition at the end
I
of each frame transmission to test functionality of the collision-detect circuitry. SQE is overridden
by SQEEN (see Table 8). SQE must be set high to interface with the TNETX3150.
TXCLK
101 111
Transmit clock. TXCLK is shared by all PHYs to clock in transmit data. Data is valid on TXD0-TDX3
O
on the edges of TXCLK specified by the currently set compatibility mode (see Table 2) or by
setting the correct bits in pin-polarity register 0x16 (see Figure 17). Functions are described in
Table 13.
TXD0
TXD1
TXD2
TXD3
119
1
32
38
58
64
I
Transmit data. Serial-data input to PHY0–PHY3.
91 101
TXEN0
TXEN1
TXEN2
TXEN3
118 128
33
39
57
63
92 102
I
Transmit enable. Assert TXEN0–TXEN3 active to indicate that valid transmit data is on
TXD0–TXD3. The active level is set by the compatibility pins (see Table 2) or by setting the correct
pins in pin-polarity register 0x16 (see Figure 17). Functions are described in Table 13.
† _{I = input, O = output, O/D = open-drain output}
6
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