TNETE2004 Datasheet, PDF (29/46 Pages) Texas Instruments – MDIO-MANAGED QuadPHY FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

mode 2 receive-data timing
tRDLAT
tPD
tCRSHO
Receive-data latency
Receive data
Time from receiver idle to carrier sense off
TNETE2004
MDIO-MANAGED QuadPHY
FOUR 10BASE-T PHYSICAL-LAYER INTERFACES
SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997
MIN TYP MAX UNIT
500
ns
40
60 ns
200
ns
RCVP/
RCVN
RXCLK
(see Note B)
tRDLAT
CRS
tPD
RXD
(see Note A)
tCRSHO
NOTES: A. During a collision, the data output on RXD is not valid received data (or looped-back transmit data) since the digital PLL is acquiring
lock to a different source of incoming data.
B. RXCLK goes high seven clock cycles after CRS goes high.
Figure 19. Mode 2 Receive Timing
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