TLC59116_1 Datasheet, PDF (6/30 Pages) Texas Instruments – 16-CHANNEL Fm+ I2C-BUS CONSTANT-CURRENT LED SINK DRIVER

TLC59116
SLDS157B – FEBRUARY 2008 – REVISED JULY 2008 .................................................................................................................................................... www.ti.com
TIMING REQUIREMENTS
T_A = –40°C to 85°C
I²C Interface
f_SCL
SCL clock frequency⁽¹⁾
t_BUF
I²C bus free time between Stop and
Start conditions
t_HD;STA
t_SU;STA
Hold time (repeated) Start condition
Setup time for a repeated Start
condition
t_SU;STO
t_HD;DAT
t_VD;ACK
t_VD;DAT
t_SU;DAT
t_LOW
t_HIGH
t_f
Setup time for Stop condition
Data hold time
Data valid acknowledge time⁽²⁾
Data valid time⁽³⁾
Data setup time
Low period of SCL clock
High period of SCL clock
Fall time of both SDA and SCL
signals ^{(4) (5)}
STANDARD MODE
I²C BUS
MIN
MAX
FAST MODE
I²C BUS
MIN
MAX
FAST MODE PLUS
I²C BUS
UNIT
MIN
MAX
0
100
0
4.7
1.3
4
0.6
4.7
0.6
4
0.6
0
0
0.3
3.45
0.1
0.3
3.45
0.1
250
100
4.7
1.3
4
0.6
300 20+0.1C_b(6)
400
0
1000 kHz
0.5
µs
0.26
µs
0.26
µs
0.26
µs
0
ns
0.9
0.05
0.45 µs
0.9
0.05
0.45 µs
50
ns
0.5
µs
0.26
µs
300
120 ns
t_r
Rise time of both SDA and SCL
signals
1000 20+0.1C_b(6)
300
120 ns
t_SP
Pulse width of spikes that must be
suppressed by the input filter⁽⁷⁾
50
50
50 ns
Reset
t_W
t_REC
t_RESET
Reset pulse width
Reset recovery time
Time to reset⁽⁸⁾⁽⁹⁾
10
10
10
ns
0
0
0
ns
400
400
400
ns
(1) Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
low for a minimum of 25 ms. Disable bus time-out feature for dc operation.
(2) t_VD;ACK = time for ACK signal from SCL low to SDA (out) low.
(3) t_VD;DAT = minimum time for SDA data out to be valid following SCL low.
(4) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V_IL of the SCL signal) in order to
bridge the undefined region of the SCL falling edge.
(5) The maximum t_f for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t_f) for the SDA output stage is specified
at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t_f.
(6) C_b = Total capacitance of one bus line in pF
(7) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
(8) Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.
(9) Upon reset, the full delay will be the sum of t_RESET and the RC time constant of the SDA bus.
6
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