TLC59116_1 Datasheet, PDF (14/30 Pages) Texas Instruments – 16-CHANNEL Fm+ I2C-BUS CONSTANT-CURRENT LED SINK DRIVER

TLC59116
SLDS157B – FEBRUARY 2008 – REVISED JULY 2008 .................................................................................................................................................... www.ti.com
Brightness Control Registers 0 to 15 (PWM0 to PWM15)
Table 5 describes Brightness Control Registers 0 to 15.
Table 5. PWM0 to PWM15 – Brightness Control Registers 0 to 15 (Address 02h to 11h) Bit Description
ADDRESS REGISTER
BIT
SYMBOL ACCESS⁽¹⁾
VALUE
DESCRIPTION
02h
PWM0
7:0
IDC0[7:0]
R/W
0000 0000⁽²⁾ PWM0 individual duty cycle
03h
PWM1
7:0
IDC1[7:0]
R/W
0000 0000⁽²⁾ PWM1 individual duty cycle
04h
PWM2
7:0
IDC2[7:0]
R/W
0000 0000⁽²⁾ PWM2 individual duty cycle
05h
PWM3
7:0
IDC3[7:0]
R/W
0000 0000⁽²⁾ PWM3 individual duty cycle
06h
PWM4
7:0
IDC4[7:0]
R/W
0000 0000⁽²⁾ PWM4 individual duty cycle
07h
PWM5
7:0
IDC5[7:0]
R/W
0000 0000⁽²⁾ PWM5 individual duty cycle
08h
PWM6
7:0
IDC6[7:0]
R/W
0000 0000⁽²⁾ PWM6 individual duty cycle
09h
PWM7
7:0
IDC7[7:0]
R/W
0000 0000⁽²⁾ PWM7 individual duty cycle
0Ah
PWM8
7:0
IDC8[7:0]
R/W
0000 0000⁽²⁾ PWM8 individual duty cycle
0Bh
PWM9
7:0
IDC9[7:0]
R/W
0000 0000⁽²⁾ PWM9 individual duty cycle
0Ch
PWM10
7:0
IDC10[7:0]
R/W
0000 0000⁽²⁾ PWM10 individual duty cycle
0Dh
PWM11
7:0
IDC11[7:0]
R/W
0000 0000⁽²⁾ PWM11 individual duty cycle
0Eh
PWM12
7:0
IDC12[7:0]
R/W
0000 0000⁽²⁾ PWM12 individual duty cycle
0Fh
PWM13
7:0
IDC13[7:0]
R/W
0000 0000⁽²⁾ PWM13 individual duty cycle
10h
PWM14
7:0
IDC14[7:0]
R/W
0000 0000⁽²⁾ PWM14 individual duty cycle
11h
PWM15
7:0
IDC15[7:0]
R/W
0000 0000⁽²⁾ PWM15 individual duty cycle
(1) R = read, W = write
(2) Default value
A 97-kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from
00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable
to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 and LEDOUT1 registers).
Duty cycle = IDCn[7:0] / 256
Group Duty Cycle Control Register (GRPPWM)
Table 6 describes the Group Duty Cycle Control Register.
Table 6. GRPPWM – Group Brightness Control Register (Address 12h) Bit Description
ADDRESS REGISTER
BIT
12h
GRPPWM
7:0
SYMBOL
GDC0[7:0]
ACCESS ⁽¹⁾
VALUE
DESCRIPTION
R/W
1111 1111⁽²⁾ GRPPWM register
(1) R = read, W = write
(2) Default value
When the DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed-frequency signal is
superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness
control, allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a Don't
care.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED
output off) to FFh (99.6% duty cycle = maximum brightness). This is applicable to LED outputs programmed with
LDRx = 11 (LEDOUT0 and LEDOUT1 registers).
When DMBLNK bit is programmed with logic 1, the GRPPWM and GRPFREQ registers define a global blinking
pattern, where GRPFREQ defines the blinking period (from 24 Hz to 10.73 s) and GRPPWM defines the duty
cycle (ON/OFF ratio in %).
Duty cycle = GDC0[7:0] / 256
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