TLC5904 Datasheet, PDF (6/27 Pages) Texas Instruments – LED DRIVER

TLC5904
LED DRIVER
SLLS391 – NOVEMBER 1999
Terminal Functions
TERMINAL
NAME
NO.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BCENA
85
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BLANK
68
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _BOUT
57
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DCLK
65
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{DIN0 – DIN7}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _DOMODE
70,71,72,73,
76,77,78,79
74
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{DOUT0 – DOUT7}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GNDANA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GNDLOG
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GNDLED
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GSCLK
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _GSOUT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _IREF
55,54,53,52,
51,49,48,47
43
84
5,10,15,20,
29,36,90,96
69
56
40
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _MCENA
46
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _MODE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _NC
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{OUT0 – OUT15}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _RSEL0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^RSEL1
83
1,2,4,6,9,11,14,16,
19,21,23,24,25,27,
28,30,31,34,35,37,
38,44,50,82,86,88,
89,91,92,95,97,98,
99
87,93,94,100,
3,7,8,12,13,
17,18,22,26,
32,33,39
66
67
I/O
DESCRIPTION
Brightness control enable. When BCENA is low, the brightness control latch is set to the
I
default value. The output current value in this status is 100% of the setting value by an
external resistor. The frequency division ratio of GSCLK is1/1. When BCENA is high,
writing to brightness control latch is enabled.
Blank(light off). When BLANK is high, all the output of the constant current driver is turned
I
off. The constant current output, which the gray scale data is not zero, is turned on (LED
on) synchronizing to the falling edge of GSCLK after the next rising edge of GSCLK when
BLANK goes from high to low.
O Blank signal delay. BOUT is the output with addition of delay time to BLANK.
Clock input for data transfer. The input data is from DIN. All data on the shift register is
I
selected by RSEL0 and RSEL1, and output data at DOUT is shifted by 1 bit synchronizing
to DCLK. The data except for DOUT is synchronized to the rising edge, and the edge for
data from DOUT is determined by the level of DOMODE.
I
Input for 8 bit parallel data. These terminals are inputs to the shift register for gray scale
data, brightness control, and OVM. The register selected is determined by RSEL0, 1.
Timing select for data output. When DOMODE is low, DOUT0–7 is changed synchronizing
I to the rising edge of DCLK. When DOMODE is high, DOUT0–7 is changed synchronizing
to the falling edge of DCLK.
Output for 8 bit parallel data with 3-state. These terminals are outputs to the shift register
O for gray scale data, brightness control, and OVM. The register selected is determined by
RSEL0, 1.
Analog ground (internally connected to GNDLOG and GNDLED)
Logic ground (internally connected to GNDANA and GNDLED)
LED driver ground (internally connected to GNDANA and GNDLOG)
I
Clock input for gray scale. The gray scale display is accomplished by lighting LEDs until
the number of GSCLK counted is equal to data latched.
O Clock delay for gray scale. GSOUT is the output with the addition of delay time to GSCLK.
Constant current value setting. LED current is set to the desired value by connecting an
I/O external resistor between IREF and GND. The 37 times current compares current across
the external resistor sink on the output terminal.
OVM enable. When MCENA is low, the OVM latch is set to the default value. The
I comparison voltage in this status is 0.3V. When MCENA is high, writing to the OVM latch
is enabled.
I
8/16 bits select. When MODE is high, 16 bits output is selected. When MODE is low, 8 bits
output is selected.
No internal connection
O Constant current output
Shift register data latch switching. When RSEL1 is low, gray scale data shift register latch
I
is selected at RSEL0 low, and the brightness control register latch is selected at RSEL0
high. When RSEL1 is high, the OVM register latch is selected at RSEL0 low, and no
register latch is selected at RSEL0 high.
6
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