TLC5510INSR Datasheet, PDF (6/15 Pages) Texas Instruments – 8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS

TLC5510, TLC5510A
8-BIT HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS
SLAS095L – SEPTEMBER 1994 – REVISED JUNE 2003
PRINCIPLES OF OPERATION
functional description
The TLC5510 and TLC5510A are semiflash ADCs featuring two lower comparator blocks of four bits each.
As shown in Figure 2, input voltage V_I(1) is sampled with the falling edge of CLK1 to the upper comparators block
and the lower comparators block(A), S(1). The upper comparators block finalizes the upper data UD(1) with the
rising edge of CLK2, and simultaneously, the lower reference voltage generates the voltage RV(1)
corresponding to the upper data. The lower comparators block (A) finalizes the lower data LD(1) with the rising
edge of CLK3. UD(1) and LD(1) are combined and output as OUT(1) with the rising edge of CLK4. As shown
in Figure 2, the output data is delayed 2.5 clocks from the analog input voltage sampling point.
Input voltage V_I(2) is sampled with the falling edge of CLK2. UD(2) is finalized with the rising edge of CLK3, and
LD(2) is finalized with the rising edge of CLK4 at the lower comparators block(B). OUT(2) data appears with
the rising edge of CLK5.
VI(1)
VI(2)
VI(3)
VI(4)
ANALOG IN
(sampling points)
CLK (clock)
Upper Comparators Block
Upper Data
Lower Reference Voltage
CLK1
CLK2
CLK3
CLK4
CLK5
S(1) C(1) S(2) C(2) S(3) C(3) S(4) C(4)
UD(0)
UD(1)
UD(2)
UD(3)
RV(0)
RV(1)
RV(2)
RV(3)
Lower Comparators Block (A)
Lower Data (A)
S(1)
H(1)
C(1) S(3)
LD(– 1)
H(3)
C(3)
LD(1)
Lower Comparators Block (B)
H(0)
C(0) S(2)
Lower Data (B)
LD(– 2)
H(2)
C(2) S(4)
H(4)
LD(0)
LD(2)
D1 – D8 (data output)
OUT(– 2)
OUT(–1)
OUT(0)
Figure 2. Internal Functional Timing Diagram
OUT(1)
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