TLC372 Datasheet, PDF (6/12 Pages) Texas Instruments – LinCMOSE DUAL DIFFERENTIAL COMPARATORS

TLC372, TLC372Q, TLC372Y
LinCMOS™ DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
electrical characteristics at specified free-air temperature, V_DD = 5 V, T_A = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
TLC372Y
UNIT
MIN
TYP MAX
VIO Input offset voltage
IIO Input offset current
IIB
Input bias current
VICR Common-mode input voltage range
VIC = VICRmin, See Note 4
0 to
VDD –1
1
5 mV
1
pA
5
pA
V
IOH High-level output current
VID = 1 V,
VOH = 5 V
0.1
nA
VOL Low-level output voltage
VID = – 1 V,
IOL = 4 mA
150 400 mV
IOL Low-level output current
VID = – 1 V,
VOL = 1.5 V
6
16
mA
IDD Supply current (two comparators)
VID = 1 V,
No load
150 300 µA
† _{All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement}
Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor
between the output and VDD. They can be verified by applying the limit value to the input and checking for the appropriate output state.
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the V_ICR test, rather than changing the input voltages, to provide greater
accuracy.
5V
1V
+
–
Applied VIO
Limit
5.1 kΩ
VO
Applied VIO
Limit
+
–
–4 V
5.1 kΩ
VO
(a) VIO WITH VIC = 0
(b) VIO WITH VIC = 4 V
Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits
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