SN74AUCH32374 Datasheet, PDF (6/11 Pages) Texas Instruments – 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
fclock
tw
tsu
th
Clock frequency
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
VCC = 0.8 V
TYP
85
5.9
1.4
0.1
VCC = 1.2 V
± 0.1 V
MIN MAX
250
1.9
1.2
0.4
VCC = 1.5 V
± 0.1 V
MIN MAX
250
1.9
0.7
0.4
VCC = 1.8 V
± 0.15 V
MIN MAX
250
1.9
0.6
0.4
VCC = 2.5 V
± 0.2 V
MIN MAX
250
1.9
0.6
0.4
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
fmax
tpd
ten
tdis
FROM
(INPUT)
CLK
OE
OE
TO
(OUTPUT)
Q
Q
Q
VCC = 0.8 V
TYP
85
VCC = 1.2 V
± 0.1 V
MIN MAX
250
VCC = 1.5 V
± 0.1 V
MIN MAX
250
7.3
1 4.5 0.8 2.9
7
1.2 5.3 0.8 3.6
8.2
2 7.1
1 4.8
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN TYP MAX MIN MAX
250
250
0.7 1.5 2.8 0.7 2.2
0.8 1.5 2.9 0.7 2.2
1.4 2.7 4.5 0.5 2.2
UNIT
MHz
ns
ns
ns
operating characteristics, T_A = 25°C^†
PARAMETER
TEST
CONDITIONS
VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V
TYP
TYP
TYP
TYP
TYP
UNIT
Cpd‡ Power
(each ^dissipation
output) ^capacitance
Outputs
enabled,
1 output
switching
1 fdata = 5 MHz
1 fclk = 10 MHz
1 fout = 5 MHz
OE = GND
CL = 0 pF
24
24
24.1
26.2
31.2
pF
Outputs 1 fdata = 5 MHz
Cpd
(Z)
Power
dissipation
capacitance
disabled,
1 clock
and 1
data
1 fclk = 10 MHz
fout = not
switching
OE = VCC
7.5
7.5
switching CL = 0 pF
8
9.4
13.2
pF
Cpd§
(each
clock)
Power
dissipation
capacitance
Outputs
disabled,
clock
only
switching
1 fdata = 0 MHz
1 fclk = 10 MHz
fout = not
switching
OE = VCC
CL = 0 pF
13.8
13.8
14
14.7
17.5
pF
† _{Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)}.}
‡ _{Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz in this}
test, but its ICC component has been subtracted out).
§ _{Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz.}
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