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CD74HC93_06 Datasheet, PDF (6/10 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Binary Ripple Counter
◁
CD74HC93, CD74HCT93
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER
HCT TYPES
Propagation Delay Time
CP0 to Q0
CP1 to Q1
CP1 to Q2
CP1 to Q3
MR1, MR2 to Qn
Output Transition Time
Input Capacitance
Power Dissipation Capacitance
TEST
VCC
25oC
-40oC TO 85oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX
tPLH, tPHL CL = 50pF
4.5 -
- 34
-
43
CL = 15pF
5
- 14 -
-
-
tPLH, tPHL CL = 50pF
4.5 -
- 34
-
43
CL = 15pF
5
-
-
-
-
-
tPLH, tPHL CL = 50pF
4.5 -
- 46
-
58
CL = 15pF
5
-
-
-
-
-
tPLH, tPHL CL = 50pF
4.5 -
- 58
-
73
CL = 15pF
5
- 24 -
-
-
tPLH, tPHL CL = 50pF
4.5 -
- 33
-
41
CL = 15pF
5
- 13 -
-
-
tTLH, tTHL CL = 50pF
4.5 -
- 15
-
19
CIN
CL = 50pF
-
-
- 10
-
10
CPD
-
-
- 25 -
-
-
-55oC TO
125oC
MIN MAX
UNITS
-
51
ns
-
-
ns
-
51
ns
-
-
ns
-
69
ns
-
-
ns
-
87
ns
-
-
ns
-
50
ns
-
-
ns
-
22
ns
-
10
pF
-
-
pF
Test Circuits and Waveforms
trCL
CLOCK
INPUT
90%
10%
tH(H)
tfCL
50%
tH(L)
DATA
INPUT
tSU(H)
tSU(L)
OUTPUT
tREM
VCC
SET, RESET
OR PRESET
tTLH
90%
tPLH
50%
tTHL
90%
50%
10%
tPHL
IC
CL
50pF
VCC
GND
VCC
50%
GND
GND
trCL
CLOCK
INPUT
2.7V
0.3V
tfCL
1.3V
tH(H)
tH(L)
DATA
INPUT
tSU(H)
1.3V
1.3V
1.3V
tSU(L)
OUTPUT
tREM
3V
SET, RESET
OR PRESET
tTLH
90%
1.3V
tPLH
1.3V
tTHL
90%
1.3V
10%
tPHL
IC
CL
50pF
3V
GND
3V
GND
GND
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 2. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
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