CD74HC93_06 Datasheet, PDF (1/10 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Binary Ripple Counter

Data sheet acquired from Harris Semiconductor
SCHS138C
August 1997 - Revised September 2003
CD74HC93,
CD74HCT93
High-Speed CMOS Logic
4-Bit Binary Ripple Counter
[ /Title
(CD74
HC93,
CD74
HCT93
)
/Sub-
ject
(High
Speed
CMOS
Logic
4-Bit
Binary
Ripple
Counte
r)
Features
Description
• Can Be Configured to Divide By 2, 8, and 16
• Asynchronous Master Reset
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
Pinout
CD74HC93
(PDIP, SOIC)
CD74HCT93
(PDIP)
TOP VIEW
CP1 1
MR1 2
MR2 3
NC 4
V_CC 5
NC 6
NC 7
14 CPO
13 NC
12 Q₀
11 Q₃
10 GND
9 Q₁
8 Q₂
The CD74HC93 and CD74HCT93 are high-speed silicon-gate
CMOS devices and are pin-compatible with low power
Schottky TTL (LSTTL). These 4-bit binary ripple counters
consist of four master-slave flip-flops internally connected to
provide a divide-by-two section and a divide- by-eight section.
Each section has a separate clock input (CP0 and CP1) to
initiate state changes of the counter on the HIGH to LOW
clock transition. State changes of the Q_n outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes.
A gated AND asynchronous master reset (MR1 and MR2 is
provided which overrides both clocks and resets (clears) all
flip-flops.
Because the output from the divide by two section is not
internally connected to the succeeding stages, the device
may be operated in various counting modes.
In a 4-bit ripple counter the output Q₀ must be connected
externally to input CP1. The input count pulses are applied
to clock input CP0. Simultaneous frequency divisions of 2, 4,
8, and 16 are performed at the Q₀, Q₁, Q₂, and Q₃ outputs
as shown in the function table. As a 3-bit ripple counter the
input count pulses are applied to input CP1.
Simultaneous frequency divisions of 2, 4, and 8 are available
at the Q₁, Q₂, Q₃ outputs. Independent use of the first flip-
flop is available if the reset function coincides with the reset
of the 3-bit ripple-through counter.
Ordering Information
PART NUMBER
CD74HC93E
CD74HC93M
CD74HC93MT
CD74HC93M96
CD74HCT93E
TEMP. RANGE
(^oC)
PACKAGE
-55 to 125
14 Ld PDIP
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld SOIC
-55 to 125
14 Ld PDIP
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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