CD74HC540 Datasheet, PDF (6/8 Pages) Texas Instruments – High Speed CMOS Logic Octal Buffer and Line Drivers, Three-State

CD74HC540, CD74HCT540, CD74HC541, CD74HCT541
Switching Specifications C_L = 50pF, Input t_r, t_f = 6ns (Continued)
PARAMETER
Three-State Output
Capacitance
TEST
SYMBOL CONDITIONS V_CC (V) MIN
C_O
-
-
20
25^oC
TYP MAX
-
20
-40^oC TO
85^oC
MIN MAX
-
20
-55^oC TO
125^oC
MIN MAX UNITS
-
20
pF
Power Dissipation Capacitance C_PD
C_L = 15pF
5
(Notes 4, 5) (540, 541)
-
55
-
-
-
-
-
pF
NOTES:
4. C_PD is used to determine the dynamic power consumption, per channel.
5. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
Test Circuits and Waveforms
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_r = 6ns
INPUT
2.7V
1.3V
0.3V
t_f = 6ns
3V
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns
OUTPUT
DISABLE
50%
OUTPUT LOW
TO OFF
t_PLZ
t_PHZ
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
90%
10%
90%
6ns
10%
t_PZL
t_PZH
OUTPUTS
DISABLED
V_CC
GND
50%
50%
OUTPUTS
ENABLED
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
t_r
6ns
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
t_PLZ
t_PHZ
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
t_f
2.7
1.3
6ns
0.3
t_PZL
3V
GND
10%
90%
t_PZH
OUTPUTS
DISABLED
1.3V
1.3V
OUTPUTS
ENABLED
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
6