CD74HC194 Datasheet, PDF (6/8 Pages) Texas Instruments – High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register

CD74HC194, CD74HCT194
Prerequisite For Switching Function (Continued)
PARAMETER
Set-up Time
S1, S0 to Clock (Figure 4)
TEST
SYMBOL CONDITIONS V_CC (V)
t_SU
-
4.5
25^oC
MIN MAX
20
-
-40^oC TO 85^oC -55^oC TO 125^oC
MIN MAX MIN MAX UNITS
25
-
30
-
ns
Set-up Time
t_SU
DSL, DSR to Clock (Figure 4)
-
4.5
14
-
18
-
21
-
ns
Hold Time
t_H
S1, S0 to Clock (Figure 4)
-
4.5
0
-
0
-
0
-
ns
Hold Time
Data to Clock (Figure 3)
t_H
-
4.5
0
-
0
-
0
-
ns
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
TEST
V_CC
SYMBOL CONDITIONS (V)
25^oC
TYP MAX
-40^oC TO 85^oC -55^oC TO 125^oC
MAX
MAX
UNITS
HC TYPES
Propagation Delay,
t_PLH, t_PHL C_L = 50pF
2
-
175
220
Clock to Output (Figure 1)
4.5
-
35
44
265
ns
53
ns
6
-
30
37
45
ns
Propagation Delay,
t_PLH, t_PHL
-
5
14
-
-
Clock to Q
-
ns
Output Transition Time
t_TLH, t_THL C_L = 50pF
2
-
75
95
(Figure 1)
4.5
-
15
19
110
ns
22
ns
6
-
13
16
19
ns
Propagation Delay,
MR to Output (Figure 2)
t_PHL
C_L = 50pF
2
-
140
175
4.5
-
28
35
210
ns
42
ns
6
-
24
30
36
ns
Input Capacitance
C_IN
-
-
-
10
10
Maximum Clock Frequency
f_MAX
-
5
60
-
-
Power Dissipation
C_PD
-
5
55
-
-
Capacitance (Notes 5, 6)
10
pF
-
MHz
-
pF
HCT TYPES
Propagation Delay,
t_PLH, t_PHL C_L = 50pF
4.5
-
37
46
Clock to Output (Figure 1)
56
ns
Propagation Delay,
t_PLH, t_PHL
-
5
15
-
-
Clock to Q
-
ns
Output Transition Times
t_TLH, t_THL C_L = 50pF
4.5
-
15
19
(Figure 1)
22
ns
Propagation Delay,
t_PHL
C_L = 50pF
4.5
-
40
50
MR to Output (Figure 2)
60
ns
Input Capacitance
C_IN
-
-
-
10
10
Maximum Clock Frequency
f_MAX
-
5
50
-
-
Power Dissipation
C_PD
-
5
60
-
-
Capacitance (Notes 5, 6)
10
pF
-
MHz
-
pF
NOTES:
5. C_PD is used to determine the dynamic power consumption, per gate.
6. P_D = V_CC2 f_i + ∑ (C_L V_CC2) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
6