CD74AC175 Datasheet, PDF (6/7 Pages) Texas Instruments – Quad D Flip-Flop with Reset

CD74AC175, CD74ACT175
Switching Specifications Input t_r, t_f = 3ns, C_L = 50pF (Worst Case) (Continued)
-40^oC TO 85^oC
-55^oC TO 125^oC
PARAMETER
SYMBOL
V_CC (V)
MIN
Propagation Delay, MR to Q, Q t_PLH, t_PHL
1.5
-
3.3
4.4
TYP
MAX
MIN
TYP
MAX UNITS
-
139
-
-
153
ns
-
15.5
4.3
-
17.1
ns
5
3.2
-
11.1
3.1
-
12.2
ns
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 13)
-
-
10
-
-
10
pF
-
55
-
-
55
-
pF
ACT TYPES
Propagation Delay, CP to Qn
t_PLH, t_PHL
5
3
(Note 12)
-
10.5
2.9
-
11.5
ns
Propagation Delay, MR to Qn
t_PLH, t_PHL
5
Input Capacitance
C_I
-
Power Dissipation Capacitance
C_PD
-
(Note 13)
3.3
-
11.8
3.3
-
13
ns
-
-
10
-
-
10
pF
-
55
-
-
55
-
pF
NOTES:
22. Limits tested 100%.
23. 3.3V Min is at 3.6V, Max is at 3V.
24. 5V Min is at 5.5V, Max is at 4.5V.
25.
CP_PDD=isCuPs_DeVd_Cto_C2def_ite+rm_Σ i(nCe_Lth+eVd_Cy_Cn2amf_oi)c+poVw_Ce_Cr
consumption
∆I_CC where f_i
per flip-flop.
= input frequency,
f_o
=
output
frequency,
C_L
=
output
load
capacitance,
V_CC
=
supply voltage.
INPUT LEVEL
CP
GND
V_S
V_S
t_W
t_PHL
V_S
V_S
t_PLH
V_S
INPUT LEVEL
MR
GND
INPUT
CP
Q
Q
V_S
V_S
t_W
t_PHL
V_S
t_REM
V_S
FIGURE 5. PROPAGATION DELAYS
INPUT LEVEL
D
GND
INPUT LEVEL
CP
GND
V_S
t_SU(L)
V_S
V_S
t_H(L)
t_SU(H)
V_S
V_S
t_H(H)
V_S
FIGURE 7.
FIGURE 6. RESET OR SET PREREQUISITE AND
PROPAGATION DELAYS
OUTPUT
DUT
R_L (NOTE)
500Ω
OUTPUT
LOAD
C_L
50pF
NOTE: For AC Series Only: When V_CC = 1.5V, R_L = 1kΩ.
Input Level
Input Switching Voltage, V_S
Output Switching Voltage, V_S
CD74AC
V_CC
0.5 V_CC
0.5 V_CC
CD74ACT
3V
1.5V
0.5 V_CC
FIGURE 8. PROPAGATION DELAY TIMES
6