CD74AC175 Datasheet, PDF (2/7 Pages) Texas Instruments – Quad D Flip-Flop with Reset

Functional Diagram
4
D0
9
CP
1
MR
5
D1
12
D2
13
D3
GND = 8
V_CC = 16
CD74AC175, CD74ACT175
D
2
Q Q0
CP
3
R ^{Q Q0}
D
7
Q Q1
CP
6
R ^{Q Q1}
D
10
Q Q2
CP
11
R ^{Q Q2}
D
15
Q Q3
CP
14
R ^{Q Q3}
TRUTH TABLE (EACH FLIP-FLOP)
INPUTS
OUTPUTS
RESET CLOCK
DATA
(MR)
CP
Dn
Qn
Qn
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
H
= High Level (Steady State)
L
= Low Level (Steady State)
X
= Irrelevant
↑
= Transition from Low to High level
Q0, Q0 = Level before the Indicated Steady-State Input conditions
were established.
2