CD54HC533 Datasheet, PDF (6/14 Pages) Texas Instruments – High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
Enable Times
(HC533)
SYMBOL
t_PZH, t_PZL
TEST
CONDITIONS
C_L = 50pF
V_CC (V)
2
4.5
25^oC
TYP MAX
-
150
-
30
-40^oC TO 85^oC
MAX
190
38
-55^oC TO
125^oC
MAX
225
45
UNITS
ns
ns
6
-
26
33
38
ns
Disable Times
(HC533)
C_L = 15pF
5
12
-
-
t_PHZ, t_PLZ
C_L = 50pF
2
-
150
190
4.5
-
30
38
-
ns
225
ns
45
ns
6
-
26
33
38
ns
C_L = 15pF
5
12
-
-
Enable and Disable Times t_PZH, t_PZL, C_L = 50pF
2
-
150
190
(HC563)
t_PHZ, t_PLZ
4.5
-
30
38
-
ns
225
ns
45
ns
6
-
26
33
38
ns
Input Capacitance
Three-State Output
Capacitance
C_L = 15pF
5
12
-
-
C_I
-
-
-
10
10
C_O
-
-
-
20
20
-
ns
10
pF
20
pF
Power Dissipation
Capacitance
(Notes 3, 4)
C_PD
-
5
42
-
-
-
pF
HCT TYPES
Propagation Delay,
Data to Qn
(HC/HCT533)
t_PLH, t_PHL
C_L = 50pF
4.5
-
34
43
C_L = 15pF
5
14
-
-
51
ns
-
ns
Propagation Delay,
Data to Qn
(HC/HCT563)
t_PLH, t_PHL
C_L = 50pF
4.5
-
30
38
C_L = 15pF
5
12
-
-
45
ns
-
ns
Propagation Delay,
LE to Qn
(HC/HCT533)
t_PLH, t_PHL
C_L = 50pF
4.5
-
38
48
C_L = 15pF
5
16
-
-
57
ns
-
ns
Propagation Delay,
LE to Qn
(HC/HCT563)
t_PZL, t_PZH
C_L = 50pF
4.5
-
35
44
C_L = 15pF
5
14
-
-
53
ns
-
ns
Enable Times
(HC/HCT533)
t_PLZ, t_PZH
C_L = 50pF
4.5
-
35
44
C_L = 15pF
5
14
-
-
Disable Times
(HC/HCT533)
t_TLH, t_THL
C_L = 50pF
4.5
-
30
38
C_L = 15pF
5
12
-
-
Enable and Disable Times t_PZH, t_PZL, C_L = 50pF
4.5
-
35
44
(HC/HCT563)
t_PHZ, t_PLZ
C_L = 15pF
5
14
-
-
Input Capacitance
C_I
-
-
-
10
10
Power Dissipation
Capacitance
(Notes 3, 4)
C_PD
-
5
42
-
-
53
ns
-
ns
45
ns
-
ns
53
ns
-
ns
10
pF
-
pF
NOTES:
3. C_PD is used to determine the no-load dynamic power consumption, per latch.
4. P_D (total power per latch) = C_PD V_CC2 f_i + Σ C_L V_CC2 f_o where f_i = Input Frequency, f_o = Output Frequency, C_L = Output Load
Capacitance, V_CC = Supply Voltage.
6