CD54HC533 Datasheet, PDF (2/14 Pages) Texas Instruments – High-Speed CMOS Logic Octal Inverting Transparent Latch, Three-State Outputs

CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563
Pinouts
CD54HC533, CD54HCT533
(CERDIP)
CD74HC533, CD74HCT533
(PDIP)
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 V_CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
CD54HC563
(CERDIP)
CD74HC563, CD74HCT563
(PDIP, SOIC)
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 V_CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Functional Block Diagram
HC/HCT533
D₀
D₁
D₂
D₃
D₄
D₅
D₆
D₇
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
DO
G
LE
OE
O₀
O₁
O₂
O₃
O₄
O₅
O₆
O₇
TRUTH TABLE
OUTPUT ENABLE
LATCH ENABLE
DATA
Q OUTPUT
L
H
H
L
L
H
L
H
L
L
l
H
L
L
h
L
H
X
X
Z
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior to
the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.
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