CD54HC4520 Datasheet, PDF (6/13 Pages) Texas Instruments – High-Speed CMOS Logic Dual Synchronous Counters

CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
HCT TYPES
TEST
SYMBOL CONDITIONS V_CC (V) MIN
25^oC
TYP MAX
-40^oC TO
85^oC
-55^oC TO 125^oC
MIN MAX MIN MAX UNITS
Propagation Delay
CP to Q_n
t_PLH,
C_L = 50pF
4.5
-
-
53
-
66
-
80
ns
t_PHL
C_L = 15pF
5
-
22
-
-
-
-
-
ns
Enable to Q_n
t_PLH,
C_L = 50pF
4.5
-
-
55
-
69
-
83
ns
t_PHL
C_L = 15pF
5
-
23
-
-
-
-
-
ns
MR to Q_n
t_PLH,
C_L = 50pF
4.5
-
-
35
-
44
-
53
ns
t_PHL
C_L = 15pF
5
-
14
-
-
-
-
-
ns
Output Transition Time
t_THL, t_TLH C_L = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
C_IN
C_L = 50pF
-
-
-
10
-
10
-
10
pF
Maximum Clock Frequency
f_MAX
CL = 15pF
5
-
50
-
-
-
-
-
MHz
Power Dissipation Capacitance
C_PD
-
(Note 3,4)
5
-
33
-
-
-
-
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per counter.
4. P_D = V_CC2 f_i (C_PD + C_L) where f_i = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
Timing Diagram
CLOCK
ENABLE
MASTER RESET
Q₁
Q₂
HC4518
Q₃
Q₄
Q₁
Q₂
’HC/HCT4520
Q₃
Q₄
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
1 2 3 4 5 6 7 8 9 01 2 3 4 5 6 7 8 9 0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4
FIGURE 1.
6