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CD54HC4520 Datasheet, PDF (5/13 Pages) Texas Instruments – High-Speed CMOS Logic Dual Synchronous Counters
◁
CD74HC4518, CD54HC4520, CD74HC4520, CD74HCT4520
Prerequisite for Switching Specifications (Continued)
25oC
PARAMETER
Set-up Time,
Enable to CP
SYMBOL
tSU
VCC (V)
2
4.5
MIN TYP
80
-
16
-
6
14
-
Removal Time,
MR to CP
tREM
2
0
-
4.5
0
-
6
0
-
Set-up Time,
CP to Enable
tSU
2
80
-
4.5
16
-
6
14
-
Removal Time,
MR to Enable
tREM
2
0
-
4.5
0
-
6
0
-
HCT TYPES
Maximum Clock
Frequency
fMAX
4.5
25
-
Clock Pulse Width
MR Pulse Width
Set-up Time,
Enable to CP
tW
4.5
20
-
tW
4.5
20
-
tSU
4.5
16
-
Removal Time,
MR tp Enable
tREM
4.5
0
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-40oC TO 85oC
MIN MAX
100
-
20
-
17
-
0
-
0
-
0
-
100
-
20
-
17
-
0
-
0
-
0
-
-55oC TO 125oC
MIN MAX
120
-
24
-
20
-
0
-
0
-
0
-
120
-
24
-
20
-
0
-
0
-
0
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
-
17
-
MHz
25
-
30
-
ns
25
-
30
-
ns
20
-
24
-
ns
0
-
0
-
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
HC TYPES
Propagation Delay
CP to Qn
Enable to Qn
MR to Qn
Output Transition Time
Input Capacitance
Maximum Clock Frequency
Power Dissipation Capacitance
(Note 3, 4)
TEST
SYMBOL CONDITIONS VCC (V) MIN
tPLH,
CL = 50pF
2
-
tPHL
CL = 50pF
4.5
-
CL = 15pF
5
-
CL = 50pF
6
-
tPLH,
CL = 50pF
2
-
tPHL
CL = 50pF
4.5
-
CL = 15pF
5
-
CL = 50pF
6
-
tPLH,
CL = 50pF
2
-
tPHL
CL = 50pF
4.5
-
CL = 15pF
5
-
CL = 50pF
6
-
tTHL, tTLH CL = 50pF
2
-
CL = 50pF
4.5
-
CL = 50pF
6
CIN
CL = 50pF
-
-
fMAX
CL = 15pF
5
CPD
CL = 15pF
5
-
25oC
TYP MAX
- 240
-
48
20
-
-
41
- 240
-
48
20
-
-
41
- 150
-
30
12
-
-
26
-
75
-
15
13
-
10
60
33
-
-40oC TO
85oC
-55oC TO 125oC
MIN MAX MIN MAX UNITS
- 300
-
-
60
-
-
-
-
-
51
-
- 300
-
-
60
-
-
-
-
-
51
-
- 190
-
-
38
-
-
-
-
-
33
-
-
95
-
-
19
-
16
-
10
-
-
-
-
360
ns
72
ns
-
ns
61
ns
360
ns
72
ns
-
ns
61
ns
225
ns
45
ns
-
ns
38
ns
110
ns
22
ns
19
ns
10
pF
MHz
-
pF
5
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