CD54HC273 Datasheet, PDF (6/13 Pages) Texas Instruments – High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD54/74HC273, CD54/74HCT273
Switching Specifications Input t_r, t_f = 6ns (Continued)
PARAMETER
Power Dissipation
Capacitance
(Notes 3, 4)
SYMBOL
C_PD
TEST
CONDITIONS V_CC (V)
-
5
25^oC
-40^oC TO 85^oC
TYP MAX
MAX
25
-
-
-55^oC TO
125^oC
MAX
-
UNITS
pF
HCT TYPES
Propagation Delay,
t_PLH, t_PHL C_L = 50pF
4.5
-
30
38
Clock to Output (Figure 4)
C_L = 15pF
5
12
-
-
Propagation Delay,
t_PHL
C_L = 50pF
4.5
-
32
40
MR to Output (Figure 4)
45
ns
-
ns
48
ns
Output Transition Time
t_TLH, t_THL C_L = 50pF
4.5
-
15
19
Input Capacitance
C_IN
-
-
-
10
10
Maximum Clock Frequency
f_MAX
C_L = 15pF
5
50
-
-
Power Dissipation
Capacitance
(Notes 3, 4)
C_PD
-
5
25
-
-
22
ns
10
pF
-
MHz
-
pF
NOTES:
3. C_PD is used to determine the dynamic power consumption, per flip-flop.
4. P_D = C_PD V_CC2 f_i + ∑ (C_L V_CC2 + f_O) where f_i = Input Frequency, f_O = Output Frequency, C_L = Output Load Capacitance, V_CC = Supply
Voltage.
Test Circuits and Waveforms
t_rC_L
CLOCK
90%
10%
t_fC_L
50%
10%
t_WL
t_WL
+
t_WH
=
I
fC_L
50%
50%
t_WH
V_CC
GND
t_rC_L = 6ns
CLOCK
2.7V
0.3V
t_fC_L = 6ns
t_WL
+
t_WH
=
I
fC_L
3V
1.3V
0.3V
1.3V
1.3V
GND
t_WL
t_WH
NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in
accordance with device truth table. For f_MAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% V_CC to 90% V_CC in
accordance with device truth table. For f_MAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
t_r = 6ns
INPUT
90%
50%
10%
t_f = 6ns
V_CC
GND
t_THL
INVERTING
OUTPUT
t_PHL
t_TLH
90%
50%
10%
t_PLH
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
t_r = 6ns
INPUT
t_THL
2.7V
1.3V
0.3V
INVERTING
OUTPUT
t_PHL
t_f = 6ns
3V
GND
t_TLH
90%
1.3V
10%
t_PLH
FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6