CD54HC273 Datasheet, PDF (5/13 Pages) Texas Instruments – High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD54/74HC273, CD54/74HCT273
Prerequisite For Switching Specifications (Continued)
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Clock Pulse Width (Figure 1)
t_W
-
2 80 -
-
100
-
120
-
ns
4.5 16 -
-
20
-
24
-
ns
6 14 -
-
17
-
20
-
ns
Set-up Time Data to Clock
t_SU
(Figure 5)
-
2 60 -
-
75
-
70
-
ns
4.5 12 -
-
15
-
18
-
ns
6 10 -
-
13
-
15
-
ns
Hold Time, Data to Clock
t_H
-
2
3
-
-
3
-
3
-
ns
(Figure 5)
4.5 3 -
-
3
-
3
-
ns
6
3
-
-
3
-
3
-
ns
Removal Time, MR to Clock
t_REM
-
2 50 -
-
65
-
75
-
ns
4.5 10 -
-
13
-
15
-
ns
6
9
-
-
11
-
13
-
ns
HCT TYPES
Maximum Clock Frequency
(Figure 2)
f_MAX
-
4.5 25 -
-
20
-
16
-
MHz
MR Pulse Width
(Figure 2)
t_w
-
4.5 12 -
-
15
-
18
-
ns
Clock Pulse Width (Figure 2)
Set-up Time Data to Clock
(Figure 6)
Hold Time, Data to Clock
(Figure 6)
Removal Time, MR to Clock
t_w
t_SU
t_H
t_REM
-
4.5 20 -
-
25
-
30
-
ns
-
4.5 12 -
-
15
-
18
-
ns
-
4.5 3 -
-
3
-
3
-
ns
-
4.5 10 -
-
13
-
15
-
ns
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
HC TYPES
Propagation Delay,
Clock to Output
(Figure 3)
TEST
SYMBOL CONDITIONS V_CC (V)
t_PLH, t_PHL C_L = 50pF
2
4.5
6
25^oC
-40^oC TO 85^oC
TYP MAX
MAX
-
150
190
-
30
38
-
26
30
-55^oC TO
125^oC
MAX
225
45
38
UNITS
ns
ns
ns
Propagation Delay,
MR to Output
(Figure 3)
C_L = 15pF
5
12
-
-
t_PHL
C_L = 50pF
2
-
150
190
4.5
-
30
38
6
-
26
30
-
ns
225
ns
45
ns
38
ns
Output Transition Time
t_TLH, t_THL C_L = 50pF
2
-
75
95
(Figure 3)
4.5
-
15
19
110
ns
22
ns
6
-
13
16
19
ns
Input Capacitance
C_I
-
-
-
10
10
Maximum Clock Frequency
f_MAX
C_L = 15pF
5
60
-
-
10
pF
-
MHz
5