CD54HC173_07 Datasheet, PDF (6/20 Pages) Texas Instruments – High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
HC TYPES
Propagation Delay, Clock to
Output
TEST
SYMBOL CONDITIONS V_CC (V)
t_PLH, t_PHL C_L = 50pF
2
4.5
25^oC
TYP MAX
-40^oC TO 85^oC -55^oC TO 125^oC
MAX
MAX
UNITS
-
200
250
-
40
50
300
ns
60
ns
C_L = 15pF
5
17
-
-
CL = 50pF
6
-
34
43
-
ns
51
ns
Propagation Delay, MR to
t_PHL
C_L = 50pF
2
-
175
220
Output
4.5
-
35
44
265
ns
53
ns
C_L = 15pF
5
12
-
-
CL = 50pF
6
-
30
37
-
ns
45
ns
Propagation Delay Output
t_PLZ, t_PHZ CL = 50pF
2
Enable to Q (Figure 6)
t_PZL, t_{PZH CL = 50pF}
4.5
150
190
30
38
C_L = 15pF
5
12
-
-
CL = 50pF
6
26
33
225
ns
45
ns
-
ns
38
ns
Output Transition Times
t_TLH, t_THL C_L = 50pF
2
-
60
75
4.5
-
12
15
90
ns
18
ns
6
-
10
13
15
ns
Maximum Clock Frequency
f_MAX
C_L = 15pF
5
60
-
-
Input Capacitance
C_IN
-
-
-
10
10
Three-State Output
Capacitance
C_O
-
-
-
10
10
-
MHz
10
pF
10
pF
Power Dissipation
Capacitance
(Notes 4, 5)
C_PD
-
5
29
-
-
-
pF
HCT TYPES
Propagation Delay, Clock to
t_PLH, t_PHL C_L = 50pF
4.5
-
40
50
Output
C_L = 15pF
5
17
-
-
Propagation Delay, MR to
t_PHL
C_L = 50pF
4.5
-
44
55
Output
C_L = 15pF
5
18
-
-
Propagation Delay Output
t_PZL, t_PZH CL = 50pF
2
Enable to Q (Figure 6)
C_L = 50pF
4.5
150
190
30
38
C_L = 15pF
5
14
-
-
CL = 50pF
6
26
33
60
ns
-
ns
66
ns
-
ns
225
ns
45
ns
-
ns
38
ns
Output Transition Times
t_TLH, t_THL C_L = 50pF
4.5
-
15
19
Maximum Clock Frequency
f_MAX
C_L = 15pF
5
60
-
-
Input Capacitance
C_IN
-
-
-
10
10
Power Dissipation
Capacitance
(Notes 4, 5)
C_PD
-
5
34
-
-
22
ns
-
MHz
10
pF
-
pF
NOTES:
4. C_PD is used to determine the dynamic power consumption, per package.
5. P_D = V_CC2 f_i + ∑ (C_L V_CC2 + f_O) where f_i = Input Frequency, f_O = Input Frequency, C_L = Output Load Capacitance, V_CC = Supply Voltage.
6