CD54HC173_07 Datasheet, PDF (5/20 Pages) Texas Instruments – High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173
DC Electrical Specifications (Continued)
PARAMETER
Three-State Leakage
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
SYMBOL
I_OZ
V_IH
V_IL
TEST
CONDITIONS
25^oC
V_I (V)
V_IL or
V_IH
I_O (mA) V_CC (V) MIN
-
6
-
TYP MAX
- ±0.5
-
-
4.5 to 2
-
-
5.5
-
-
4.5 to -
- 0.8
5.5
-40^oC TO 85^oC
MIN MAX
-
±0.5
2
-
-
0.8
High Level Output
Voltage
CMOS Loads
V_OH
V_IH or -0.02
4.5
4.4
-
-
4.4
-
V_IL
High Level Output
Voltage
TTL Loads
-6
4.5 3.98 -
-
3.84
-
Low Level Output
Voltage
CMOS Loads
V_OL
V_IH or 0.02
4.5
-
- 0.1
-
0.1
V_IL
Low Level Output
Voltage
TTL Loads
6
4.5
-
- 0.26
-
0.33
Input Leakage
Current
I_I
V_CC to
0
5.5
-
- ±0.1
-
±1
GND
Quiescent Device
Current
I_CC
V_CC or
0
5.5
-
-
8
-
80
GND
Additional Quiescent
∆I_CC
V_CC
-
4.5 to - 100 360
-
450
Device Current Per
(Note 3) -2.1
5.5
Input Pin: 1 Unit Load
Three-State Leakage
I_OZ
V_IL or
-
Current
V_IH
5.5
-
- ±0.5
-
±5.0
NOTE:
3. For dual-supply systems theoretical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
-55^oC TO 125^oC
MIN MAX UNITS
-
±10
µA
2
-
V
-
0.8
V
4.4
-
V
3.7
-
V
-
0.1
V
-
0.4
V
-
±1
µA
-
160
µA
-
490
µA
-
±10
µA
HCT Input Loading Table
INPUT
UNIT LOADS
D0-D3
0.15
E1 and E2
0.15
CP
0.25
MR
0.2
OE1 and OE2
0.5
NOTE: Unit Load is
Specifications table,
∆I_CC
e.g.,
limit specified
360µA max at
in DC
25^oC.
Electrical
5