CC8520 Datasheet, PDF (6/17 Pages) Texas Instruments – 2.4 GHz RF SoC FOR WIRELESS DIGITAL AUDIO STREAMING CC8520 - PurePath™ Wireless

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CC8520
SWRS091A – MARCH 2010
PIN PIN NAME PIN TYPE
DESCRIPTION
10
IODVDD
Power
(I/O pads)
Digital power supply for the digital I/Os in the SPI interface and GIO1-GIO3.
11 RSTN
Digital Input
(pull-up)
Active-low device reset
12 IOVDD
13 MCLK
Power
(I/O pins)
Digital I/O¹
Digital power supply for the RSTN and MCLK digital I/O pins.
Master clock output for external audio devices
GIO4
14 BCLK
Digital I/O¹
General-purpose digital I/O pin 4
I2S/DSP audio interface bit clock (in/out)
GIO5
15 WCLK
Digital I/O¹
General-purpose digital I/O pin 5
I2S/DSP audio interface word clock (in/out)
GIO6
16 AD0
Digital I/O¹
General-purpose digital I/O pin 6
I2S/DSP audio interface data line 0 (in/out)
GIO7
17 AD1
Digital I/O¹
General-purpose digital I/O pin 7
I2S/DSP audio interface data line 1 (in/out)
GIO8
General-purpose digital I/O pin 8
18 IOVDD
19 AD2
Power
(I/O pins)
Digital I/O²
Digital power supply for the digital I/Os in audio interface (BCLK-AD2).
I2S/DSP audio interface data line 2 (in/out)
GIO9
Configurable with PurePath™ Wireless Configurator
20 AVDD
Power (Analog) 2.0-3.6V analog power supply connection
21 XI
Analog I/O
Crystal oscillator pin input, or external clock input (48 MHz)
22 XO
Analog I/O
Crystal oscillator pin output (48 MHz)
23 AVDD
Power (Analog) Analog power supply connection
24 RF_P
RF I/O
Positive differential RF input signal to LNA in receive mode
Positive differential RF output signal from PA in transmit mode
25 RF_N
RF I/O
Negative differential RF input signal to LNA in receive mode
Negative differential RF output signal from PA in transmit mode
26 AVDD
Power (Analog) Analog power supply connection
27 AVDD
Power (Analog) Analog power supply connection
28 AVDD
Power (Analog) Analog power supply connection
29 VBAT
Analog input
Battery voltage supervisor (threshold level programmable by external resistor to positive
battery terminal)
30 RBIAS
Analog output
External precision bias resistor for reference current. 56 kΩ, ±1%
31 AVDD
32 SCL
Power (Analog)
Digital I/O¹
Analog power supply connection (Guard ring AVDD connection for digital noise isolation)
I2C master clock line. Must be connected to external pull-up
GIO10
33 SDA
Digital I/O¹
General-purpose digital I/O pin 10
I2C master data line. Must be connected to external pull-up
GIO11
34 GIO12
Digital I/O¹
35 GIO13
Digital I/O¹
36
XLNAEN
Digital I/O²
General-purpose digital I/O pin 11
General-purpose digital I/O pin 12
General-purpose digital I/O pin 13
Control external LNA
37
IODVDD
Power (I/O pads) Digital power supply for SCL-GIO15 pins.
38 XPAEN
Digital I/O²
Control external PA
6
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