TSB43AB22A Datasheet, PDF (59/112 Pages) Texas Instruments – INTEGRATED 1394A-2000 OHCI PHY/LINK-LAYER CONTROLLER

BIT
23
22
21
20
19
18
17
16
15
14–10
9
8
7
6
5
4
3
2
1
0
Table 4–15. Interrupt Event Register Description (Continued)
FIELD NAME
cycleInconsistent
TYPE
RSCU
DESCRIPTION
A cycle start was received that had values for the cycleSeconds and cycleCount fields that are
different from the values in bits 31–25 (cycleSeconds field) and bits 24–12 (cycleCount field) in the
isochronous cycle timer register at OHCI offset F0h (see Section 4.34, Isochronous Cycle Timer
Register).
cycleLost
cycle64Seconds
cycleSynch
RSCU
RSCU
RSCU
A lost cycle is indicated when no cycle_start packet is sent or received between two successive
cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately
follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after
a cycleSynch event without an intervening cycle start. Bit 22 may be set to 1 either when a lost cycle
occurs or when logic predicts that one will occur.
Indicates that the 7th bit of the cycle second counter has changed.
Indicates that a new isochronous cycle has started. Bit 20 is set to 1 when the low-order bit of the
cycle count toggles.
phy
regAccessFail
RSCU
RSCU
Indicates that the PHY layer requests an interrupt through a status transfer.
Indicates that a TSB43AB22A register access has failed due to a missing SCLK clock signal from
the PHY layer. When a register access fails, bit 18 is set to 1 before the next register access.
busReset
selfIDcomplete
RSCU
RSCU
Indicates that the PHY layer has entered bus reset mode.
A self-ID packet stream has been received. It is generated at the end of the bus initialization process.
Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on.
selfIDcomplete2
RSCU Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1 by the TSB43AB22A
device when it sets bit 16 (selfIDcomplete), and retains the state, independent of bit 17 (busReset).
RSVD
lockRespErr
R
RSCU
Reserved. Bits 14–10 return 0s when read.
Indicates that the TSB43AB22A device sent a lock response for a lock request to a serial bus register,
but did not receive an ack_complete.
postedWriteErr
RSCU Indicates that a host bus error occurred while the TSB43AB22A device was trying to write a 1394
write request, which had already been given an ack_complete, into system memory.
isochRx
isochTx
RU Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have
generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous
receive interrupt event register at OHCI offset A0h/A4h (see Section 4.25, Isochronous Receive
Interrupt Event Register) and isochronous receive interrupt mask register at OHCI offset A8h/ACh
(see Section 4.26, Isochronous Receive Interrupt Mask Register). The isochronous receive interrupt
event register indicates which contexts have been interrupted.
RU Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have
generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous
transmit interrupt event register at OHCI offset 90h/94h (see Section 4.23, Isochronous Transmit
Interrupt Event Register) and isochronous transmit interrupt mask register at OHCI offset 98h/9Ch
(see Section 4.24, Isochronous Transmit Interrupt Mask Register). The isochronous transmit
interrupt event register indicates which contexts have been interrupted.
RSPkt
RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the
descriptor xferStatus and resCount fields have been updated.
RQPkt
RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the
descriptor xferStatus and resCount fields have been updated.
ARRS
RSCU Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1 upon completion of an
ARRS DMA context command descriptor.
ARRQ
RSCU Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1 upon completion of an
ARRQ DMA context command descriptor.
respTxComplete
RSCU Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to 1 upon completion of an
ATRS DMA command.
reqTxComplete
RSCU Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1 upon completion of an
ATRQ DMA command.
4–19