TSB43AB22A Datasheet, PDF (25/112 Pages) Texas Instruments – INTEGRATED 1394A-2000 OHCI PHY/LINK-LAYER CONTROLLER

3.5 Status Register
The status register provides status over the TSB43AB22A interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3–4 for a complete
description of the register contents.
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Name
Status
Type
RCU RCU RCU RCU RCU R
R RCU R
R
R
R
R
R
R
R
Default 0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
BIT
15
14
13
12
11
10–9
8
7
6
5
4
3–0
Register:
Offset:
Type:
Default:
Status
06h
Read/Clear/Update, Read-only
0210h
Table 3–4. Status Register Description
FIELD NAME
PAR_ERR
SYS_ERR
MABORT
TABORT_REC
TABORT_SIG
PCI_SPEED
DATAPAR
FBB_CAP
UDF
66MHZ
CAPLIST
RSVD
TYPE
RCU
RCU
RCU
RCU
RCU
R
RCU
R
R
R
R
R
DESCRIPTION
Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.
Signaled system error. Bit 14 is set to 1 when PCI_SERR is enabled and the TSB43AB22A device has
signaled a system error to the host.
Received master abort. Bit 13 is set to 1 when a cycle initiated by the TSB43AB22A device on the PCI
bus has been terminated by a master abort.
Received target abort. Bit 12 is set to 1 when a cycle initiated by the TSB43AB22A device on the PCI
bus was terminated by a target abort.
Signaled target abort. Bit 11 is set to 1 by the TSB43AB22A device when it terminates a transaction
on the PCI bus with a target abort.
DEVSEL timing. Bits 10 and 9 encode the timing of PCI_DEVSEL and are hardwired to 01b, indicating
that the TSB43AB22A device asserts this signal at a medium speed on nonconfiguration cycle
accesses.
Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:
a. PCI_PERR was asserted by any PCI device including the TSB43AB22A device.
b. The TSB43AB22A device was the bus master during the data parity error.
c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space
(see Section 3.4, Command Register) is set to 1.
Fast back-to-back capable. The TSB43AB22A device cannot accept fast back-to-back transactions;
therefore, bit 7 is hardwired to 0.
User-definable features (UDF) supported. The TSB43AB22A device does not support the UDF;
therefore, bit 6 is hardwired to 0.
66-MHz capable. The TSB43AB22A device operates at a maximum PCI_CLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
Capabilities list. Bit 4 returns 1 when read, indicating that capabilities additional to standard PCI are
implemented. The linked list of PCI power-management capabilities is implemented in this function.
Reserved. Bits 3–0 return 0s when read.
3–5