TSB42AC3 Datasheet, PDF (58/70 Pages) Texas Instruments – General purpose link layer ideal for a wide-range of applications

BCLK
0
(Input)
(see Note A)
ÏÏÏ ADDR0 −
ADDR7
ÏÏÏ _(Input)
td3
DATA0 −
DATA31
(Output)
1
2
8
DATA1
td4
DATA2
DATA7
DATA8
CS
(Input)
ÏÏÏ _WR
ÏÏÏÏÏÏ (Input)
td1
CA
(Output)
(see Note B)
NOTES: A. At the (nth+1) BCLK rising edge, the host bus should latch DATAn.
B. CA is one cycle delay from respective CS.
C. These waveforms only apply to address C0h.
Figure 6−7. Burst Read Waveforms
9
10
DATA9
td2 ^{ÏÏÏÏÏÏÏÏÏÏÏÏ}
SCLK 50%
(Input)
tw2(H)
50% 50%
tw2(L)
tc2
Figure 6−8. SCLK Waveform
SCLK 50%
(Input)
td5
50%
td6
50%
td7
D0 − D7
(Output
)
td8
td9
td10
CTL0 − CTL1
(Output)
Figure 6−9. TSB42AC3-to-PHY Layer Interface Transfer Waveforms
4
TSB42AC3
SLLS593A—January 2006