TSB42AC3 Datasheet, PDF (30/70 Pages) Texas Instruments – General purpose link layer ideal for a wide-range of applications

Internal Registers
Example 1−4 only requires one host bus write transaction. The packet is stored in the ATF in the following
format:
{1, DATA1[0:31]}
{0, DATA2[0:31]}
{0, DATA3[0:31]}
.
.
{0, DATA(n−1)[0:31]}
{0, DATAn[0:31]}
3.3.3 ITF Access
The procedure to access to the ITF through 90h, 94h, and 9Ch is as follows:
1. Write the first quadlet of the packet to ITF location 90h and set the control bit to 1 to indicate the first quadlet
of the packet, the data is not confirmed for transmission.
2. Write second to n−1 quadlets of the packet to ITF location 94h. Burst write can be used to write n−2
quadlets into ITF, which requires only one host write transaction, the data is not confirmed for
transmission.
3. Write the last quadlet of the packet to ITF location 9Ch. It supports burst write, which allows multiple
quadlets to load into ITF. The data is confirmed for transmission. If consecutive writes to ITF_Continue
and update does not keep up with the data being put on the 1394 bus, an ITF underflow error occurs.
If the first quadlet of a packet is not written to the ITF_FIRST, the transmitter enters a state denoted by an
ITFBadF interrupt. An underflow of the ITF also causes an ITFBadF interrupt. When this state is entered, no
isochronous packets can be sent until the ITF is cleared by the ClrITF control bit. Asynchronous packets can
be sent while in this state.
The procedure to access the ITF through B0h is as follows:
• Write to address B0h (ITF burst write) writes the whole packet into ITF. The first quadlet written into ITF
has the control bit set to 1 to indicate this is the first quadlet of the packet. The termination of the burst
write on the host interface confirms the packet for transmission.
ITF access example:
Assume there are n quadlets needed to write to ITF for transmission.
Example 1−5. Non-Burst Write
90h (ITF_First)
94h (ITF_Continue)
.
.
94h (ITF_Continue)
9Ch (ITF_Continue & Update)
DATA1[0:31]
DATA2[0:31]
.
.
DATA(n−1)[0:31]
DATAn[0:31]
Example 1−6. Allowable Burst Write
90h (ITF_First)
94h (ITF_Continue) (burst write)
.
.
94h (ITF_Continue) (burst write)
9Ch (ITF_Continue & Update)
DATA1[0:31]
DATA2[0:31]
.
.
DATA(n−1)[0:31]
DATAn[0:31]
16 TSB42AC3
SLLS593A—January 2006