ADC12D1000CIUT Datasheet, PDF (54/73 Pages) Texas Instruments – ADC12D1000/ADC12D1600 12-Bit, 2.0/3.2 GSPS Ultra High-Speed ADC

ADC12D1000, ADC12D1600
SNAS480M – MAY 2010 – REVISED MARCH 2013
www.ti.com
CLK Level
The input clock amplitude is specified as V_{IN_CLK} in Converter Electrical Characteristics Sampling Clock
Characteristics . Input clock amplitudes above the max V_{IN_CLK} may result in increased input offset voltage. This
would cause the converter to produce an output code other than the expected 2047/2048 when both input pins
are at the same potential. Insufficient input clock levels will result in poor dynamic performance. Both of these
results may be avoided by keeping the clock input amplitude within the specified limits of V_{IN_CLK}.
CLK Duty Cycle
The duty cycle of the input clock signal can affect the performance of any A/D converter. The ADC12D1000/1600
features a duty cycle clock correction circuit which can maintain performance over the 20%-to-80% specified
clock duty-cycle range. This feature is enabled by default and provides improved ADC clocking, especially in the
Dual-Edge Sampling (DES) Mode.
CLK Jitter
High speed, high performance ADCs such as the ADC12D1000/1600 require a very stable input clock signal with
minimum phase noise or jitter. ADC jitter requirements are defined by the ADC resolution (number of bits),
maximum ADC input frequency and the input signal amplitude relative to the ADC input full scale range. The
maximum jitter (the sum of the jitter from all sources) allowed to prevent a jitter-induced reduction in SNR is
found to be
t_J(MAX) = ( V_IN(P-P)/ V_FSR) x (1/(2^(N+1) x π x f_IN))
(3)
where t_J(MAX) is the rms total of all jitter sources in seconds, V_IN(P-P) is the peak-to-peak analog input signal, V_FSR
is the full-scale range of the ADC, "N" is the ADC resolution in bits and f_IN is the maximum input frequency, in
Hertz, at the ADC analog input.
t_J(MAX) is the square root of the sum of the squares (RSS) of the jitter from all sources, including: the ADC input
clock, system, input signals and the ADC itself. Since the effective jitter added by the ADC is beyond user
control, it is recommended to keep the sum of all other externally added jitter to a minimum.
CLK Layout
The ADC12D1000/1600 clock input is internally terminated with a trimmed 100Ω resistor. The differential input
clock line pair should have a characteristic impedance of 100Ω and (when using a balun), be terminated at the
clock source in that (100Ω) characteristic impedance.
It is good practice to keep the ADC input clock line as short as possible, tightly coupled, keep it well away from
any other signals, and treat it as a transmission line. Otherwise, other signals can introduce jitter into the input
clock signal. Also, the clock signal can introduce noise into the analog path if it is not properly isolated.
THE LVDS OUTPUTS
The Data, ORI, ORQ, DCLKI and DCLKQ outputs are LVDS. The electrical specifications of the LVDS outputs
are compatible with typical LVDS receivers available on ASIC and FPGA chips; but they are not IEEE or ANSI
communications standards compliant due to the low +1.9V supply used on this chip. These outputs should be
terminated with a 100Ω differential resistor placed as closely to the receiver as possible. If the 100Ω differential
resistance is built in to the receiver, then an externally placed resistor is not necessary. This section covers
common-mode and differential voltage, and data rate.
Common-mode and Differential Voltage
The LVDS outputs have selectable common-mode and differential voltage, V_OS and V_OD; see Digital Control and
Output Pin Characteristics. See Output Control and Adjust for more information.
Selecting the higher V_OS will also increase V_OD slightly. The differential voltage, V_OD, may be selected for the
higher or lower value. For short LVDS lines and low noise systems, satisfactory performance may be realized
with the lower V_OD. This will also result in lower power consumption. If the LVDS lines are long and/or the system
in which the ADC12D1000/1600 is used is noisy, it may be necessary to select the higher V_OD.
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