TMS320C6472 Datasheet, PDF (53/65 Pages) Texas Instruments – Digital Signal Processor Silicon Revisions 2.0 1.2 1.1 1.0

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Silicon Revision 1.2 Usage Notes and Known Design Exceptions to Functional Specifications
Advisory 23
DMA Access to L2 SRAM May Stall When the DMA Has Lower Priority Than the
CPU
Revision(s) Affected:
Details:
1.2, 1.1, 1.0
The L2 memory controller in the GEM has programmable bandwidth management
features that are used to control bandwidth allocation for all requestors. There are two
parameters to control this, command priority and arbitration counter MAXWAIT values.
Each requestor has a command priority and the requestor with the higher priority wins.
However, there are also counters associated with each requestor that track the number
of cycles each requestor loses arbitration. When this counter reaches a threshold
(MAXWAIT), which is programmed by the user (or default value), the losing requestor
gets an arbitration slot and wins for that cycle. There are four such requestors: CPU,
DMA (SDMA and IDMA), user cache coherency operation, and global cache coherence.
Global-coherence operations are highest priority, while user-coherence operations are
lowest priority. However, there is active arbitration done for the CPU and the DMA
(SDMA/IDMA) commands. The priority for DMA commands comes from an external
master as part of the SDMA command or a programmable register, IDMA1_COUNT, in
the GEM for IDMA commands. The priority for CPU accesses to L2 is in a
programmable register, CPUARBU, in the GEM. For the default priority values, see
Table 14.
More details on the bandwidth management feature can be found in the C64x+
Megamodule Reference Guide (SPRU871).
Table 14. C6472 Default Master Priorities
MASTER
EDMA3TCx
SRIO (Data Access)
EMAC
HPI
UTOPIA - PDMA
TSIP
C64x+ Megamodule (MDMA port)
C64x+ Megamodule (CPU Arbitration
control to L2)
C64x+ Megamodule (IDMA channel 1)
DEFAULT MASTER PRIORITIES
(0 = Highest priority,
7 = Lowest priority)
0
0
7
7
1
7
7
1
PRIORITY CONTROL
QUEPRI.PRIQx (EDMA3 register)
PER_SET_CNTL.CBA_TRANS_PRI (SRIO register)
PRI_ALLOC.EMAC
PRI_ALLOC.HOST
PRI_ALLOC.UTOPIAPDMA
DMACTL (TSIP register)
MDMAARBE.PRI (C64x+ Megamodule register)
CPUARBU (C64x+ Megamodule register)
0
IDMA1_COUNT (C64x+ Megamodule register)
To enable bandwidth management, the L2 memory controller has an internal (non-user
visible) counter that counts MAXWAIT every cycle that a DMA command is blocked
because of a CPU access. When the internal counter reaches the MAXWAIT threshold,
it is supposed to stay saturated at that value and force the DMA access to win arbitration
over the CPU. In the case where DMA priority is less than CPU priority, the internal
counter does not saturate at the MAXWAIT threshold value. Instead, it wraps around and
keeps counting, thereby, giving more bandwidth to the CPU than intended by the
MAXWAIT threshold value. The result is that the DMA may lose to the CPU over multiple
arbitration cycles. This typically happens when CPU accesses keep the L2 memory
controller busy every cycle; for example, a continuous stream of L1D write misses to L2.
Workaround:
Set the CPU at a lower priority than the DMA commands to L2. The priority for CPU
accesses to L2 is in a programmable register, CPUARBU, in the GEM. However,
lowering the CPU priority may impact the performance since CPU accesses to L2 may
stall due to DMA accesses, in case of contention.
This bug has been fixed on silicon revision 2.0.
SPRZ300 – October 2009
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TMS320C6472 DSP 53
Silicon Revisions 2.0, 1.2, 1.1, 1.0