TMS320C6472 Datasheet, PDF (16/65 Pages) Texas Instruments – Digital Signal Processor Silicon Revisions 2.0 1.2 1.1 1.0

Silicon Revision 2.0 Usage Notes and Known Design Exceptions to Functional Specifications
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Advisory 20
DDR2 EMIF Buffers Not Totally Compensated by Default
Revision(s) Affected:
Details:
Workaround:
2.0, 1.2, 1.1, 1.0
The output buffers on the DDR2 EMIF contain dynamic impedance compensation
circuitry to maintain a constant output impedance across temperature, voltage, and
silicon process variation. This impedance compensation circuitry must configure each
individual output buffer. The output buffer compensation for each DDR2 output buffer is
not complete until both a 1-to-0 and 0-to-1 transition has occurred on that output.
Until this compensation occurs, the output drive strength is probably less than ideal. The
DDR2 EMIF cycles that occur before dynamic compensation is complete may fail. Since
the mode register (MR) write cycles are the first cycles initiated by the DDR2 EMIF after
a reset, these cycles are at risk. Similarly, after EMIF configuration, the first writes to
DDR2 memory are also at risk.
This issue has not been seen in the field. It has only been observed on test fixtures at TI.
Therefore, it appears to have a very low probability of affecting existing designs. The
recommended topologies that only have one or two loads per DDR2 EMIF without VTT
termination appear to be resilient to this condition. The possibility of failure can only be
eliminated if the software workaround described below is implemented.
Some system start-up sequences improve the probability of robust operation, such as:
• Incomplete compensation may cause mode register (MR) writes to fail. This could
result in DDR2 performance lower than expected or complete failure. The risk of this
occurring is reduced through multiple MR write operations since compensation of
most address and control output buffers and both clock output buffers are completed
before the final MR write. Most DDR2 EMIF configuration sequences, including the
one implemented in the CSL, result in multiple MR write operations. MR write cycles
are also designed to complete on the slowest possible DDR2 memory devices. This
is another reason these cycles have a high probability of success.
• Incomplete compensation may cause initial DDR2 memory writes to fail. This could
cause the DSP to execute incorrectly if these initial writes are code or critical data.
Many system implementations use a secondary bootloader to load the full binary
image. The secondary bootloader is then discarded after boot completion. Therefore,
any invalid writes would occur in the bootloader and the full application code is
loaded after the DDR2 EMIF output buffers have been activated many times. (This is
not a full guarantee of complete compensation but the probability is high that all of
the output buffers are fully compensated by the time the secondary bootloader is
written.)
• A better guarantee that this compensation has no latent impact is validation of the full
binary image through some type of code checksum at the end of the boot process. If
the code is verified in this way, the system is guaranteed to be robust.
This workaround has to be executed every time the DDR2 EMIF is initialized. Since it
should occur before valid mode register writes can be completed, the EMIF configuration
has to be repeated after the output buffers are fully compensated. The sequence of
steps listed below completes the dynamic compensation for all of the DDR2 EMIF output
buffers. The CSL API function CSL_ddr2HwSetup is called during the normal bring-up
process to trigger MR writes. Therefore, the workaround code can be put before the API
function call.
16 TMS320C6472 DSP
Silicon Revisions 2.0, 1.2, 1.1, 1.0
Copyright © 2009, Texas Instruments Incorporated
SPRZ300 – October 2009
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