ADS62C17 Datasheet, PDF (53/68 Pages) Texas Instruments – Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost

ADS62C17
www.ti.com ............................................................................................................................................................. SLAS631A – APRIL 2009 – REVISED JULY 2009
Table 13. Power Down Controls
POWER DOWN MODES
Normal operation
Output buffer disabled for channel B
Output buffer disabled for channel A
Output buffer disabled for channel A and B
Global power down
Channel B standby
Channel A standby
Multiplexed (MUX) mode – Output data of channel A
and B is multiplexed & available on DA10 to DA0
pins.
CONFIGURE USING
SERIAL INTERFACE
PARALLEL CONTROL
PINS
WAKE-UP
TIME
<POWER DOWN MODES>=0000
low low
low
–
<POWER DOWN MODES>=1001
<POWER DOWN MODES>=1010
<POWER DOWN MODES>=1011
The pins do not
support output buffer
disable
–
–
Fast (100 ns)
<POWER DOWN MODES>=1100
high low
low Slow (20 µs)
<POWER DOWN MODES>=1101
high low high Fast (1 µs)
<POWER DOWN MODES>=1110
high high low Fast (1 µs)
<POWER DOWN MODES>=1111
high high high
–
Power Down Global
In this mode, the entire chip including both the A/D converters, internal reference and the output buffers are
powered down resulting in reduced total power dissipation of about 45mW. The output buffers are in high
impedance state. The wake-up time from the global power down to data becoming valid in normal mode is
typically 20 µs.
Channel Power Down (individual or both channels)
Here, each channel’s A/D converter can be powered down. The internal references are active, resulting in quick
wake-up time of 1 µs. The total power dissipation in standby is about 450 mW.
Output Buffer Disable (individual or both channels)
Each channel’s output buffer can be disabled and put in high impedance state – wakeup time from this mode is
fast, about 100 ns.
Input Clock Stop
In addition to the above, the converter enters a low-power mode when the input clock frequency falls below
1MSPS. The power dissipation is about 275 mW.
POWER SUPPLY SEQUENCE
During power-up, the AVDD and DRVDD supplies can come up in any sequence. The two supplies are
separated in the device.
DIGITAL OUTPUT INTERFACE
ADS62C17 provides 11-bit data and an output clock synchronized with the data.
Two output interface options are available – Double Data Rate (DDR) LVDS and parallel CMOS. They can be
selected using the serial interface register bit <LVDS_CMOS> or using DFS pin in parallel configuration mode.
DDR LVDS Interface
In this mode, the data bits and clock are output using LVDS (Low Voltage Differential Signal) levels. Two data
bits are multiplexed and output on each LVDS differential pair.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS62C17
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