ADS62C17 Datasheet, PDF (52/68 Pages) Texas Instruments – Dual Channel 11 Bit, 200 MSPS ADC With SNRBoost

ADS62C17
SLAS631A – APRIL 2009 – REVISED JULY 2009 ............................................................................................................................................................. www.ti.com
Table 12. Time Constant of Offset Correction Algorithm
<OFFSET CORR TIME
CONSTANT>
D3-D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Time Constant (TCCLK),
Number of Clock Cycles
256 k
512 k
1M
2M
4M
8M
16 M
32 M
64 M
128 M
256 M
512 M
RESERVED
RESERVED
RESERVED
RESERVED
Time Constant, sec
(=TC_CLK x 1/Fs)⁽¹⁾
1.2 ms
2.5 ms
5 ms
10 ms
20 ms
40 ms
80 ms
0.16 s
0.32 s
0.64 s
1.28 s
2.5 s
(1) Sampling frequency, Fs = 200 MSPS
1026
1025
Offset correction
1024 _disabled
Offset correction
enabled
Output data with
offset corrected
1023
1022
1021
1020
Output data with
1019 _{4 LSB offset}
1018
-2
0
2
4
6
8 10 12 14 16 18 20
Time - ms
Figure 56. Time Response of Offset Correction
POWER DOWN
ADS62C17 has three power down modes – power down global, individual channel standby and individual
channel output buffer disable. These can be set using either the serial register bits or using the control pins
CTRL1 to CTRL3.
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