LM3S9B90_11 Datasheet, PDF (519/1295 Pages) Texas Instruments – LM3S9B90 Microcontroller

Stellaris® LM3S9B90 Microcontroller
Register 5: EPI Host-Bus 16 Configuration (EPIHB16CFG), offset 0x010
Important: The MODE field in the EPICFG register determines which configuration register is
accessed for offsets 0x010 and 0x014.
To access EPIHB16CFG, the MODE field must be 0x3.
The Host Bus 16 sub-configuration register is activated when the HB16 mode is selected. The HB16
mode supports muxed address/data (overlay of lower 16 address and all 16 data pins), separated
address/data, and address-less FIFO mode. Note that this register is reset when the MODE field in
the EPICFG register is changed. If another mode is selected and the HB16 mode is selected again,
the values must be reinitialized.
This mode is intended to support SRAMs, Flash memory (read), FIFOs, and CPLDs/FPGAs, and
devices with an MCU/HostBus slave or 16-bit FIFO interface support.
Refer to Table 10-6 on page 492 for information on signal configuration controlled by this register
and the EPIHB16CFG2 register.
If less address pins are required, the corresponding AFSEL bit (page 446) should not be enabled so
the EPI controller does not drive those pins, and they are available as standard GPIOs.
There is no direct chip enable (CE) model. Instead, CE can be handled in one of three ways:
1. Manually control via GPIOs.
2. Associate one or more upper address pins to CE. Because CE is normally CEn, lower addresses
are not used. For example, if pins EPI0S27 and EPI0S26 are used for Device 1 and 0
respectively, then address 0x6800.0000 accesses Device 0 (Device 1 has its CEn high), and
0x6400.0000 accesses Device 1 (Device 0 has its CEn high). The pull-up behavior on the
corresponding GPIOs must be properly configured to ensure that the pins are disabled when
the interface is not in use.
3. With certain SRAMs, the ALE can be used as CEn because the address remains stable after
the ALE strobe. The subsequent WRn or RDn signals write or read when ALE is low thus
providing CEn functionality.
EPI Host-Bus 16 Configuration (EPIHB16CFG)
Base 0x400D.0000
Offset 0x010
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
reserved
Type RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
15
14
13
12
11
10
9
MAXWAIT
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
24
23
22
21
20
19
18
17
16
XFFEN XFEEN WRHIGH RDHIGH
reserved
RO
R/W
R/W
R/W
R/W
RO
RO
RO
RO
0
0
0
0
0
0
0
0
0
8
R/W
0
7
6
WRWS
R/W
R/W
0
0
5
4
RDWS
R/W
R/W
0
0
3
reserved
RO
0
2
BSEL
R/W
0
1
0
MODE
R/W
R/W
0
0
Bit/Field
31:24
Name
reserved
Type
RO
Reset
0x00
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
March 19, 2011
519
Texas Instruments-Advance Information