TSB12LV41 Datasheet, PDF (50/195 Pages) Texas Instruments – IEEE 1394-1995 Link-Layer Controller for Consumer Applications

General Asynchronous Receive Notes
• Every correctly received asynchronous lock/write request received by the bulky asynchronous
receive FIFO (BARX) is acknowledged by sending either an ack_complete (0001b) or an
ack_pending (0010b). Register 148, bit 17 (BAckPendEn) programs the ack response code. For
packets received to the asynchronous control receive FIFO (ACRX), the response code can be
programmed in register C, bit 13 (AckPendEn).
• All correctly received read request packets are acknowledged with Ack_Pending (BusyX).
• Whenever an asynchronous packet is not received correctly to the BARX or ACRX, an
Ack_Data_Error (1101b) response is sent regardless of the value of BackPendEn (or
AckPendEn). This occurs anytime the data CRC check fails or there is a mismatch between the
actual payload and the data length in the header.
3.2.2 Receiving Isochronous Packets
When the MPEG2Lynx receives an isochronous packet, the isochronous header and trailer quadlets are
automatically copied to registers 140h and 144h (IRT and IRH). The isochronous trailer is a quadlet inserted
by the receiving MPEG2Lynx at the end of a received packet. It gives information on the packet speed,
number of padding bits, and whether or not the packet was received correctly.
The isochronous packet is then received into the bulky isochronous receive FIFO (BIRX). The size for the
BIRX can be set in register 12Ch (bulky isochronous size register.) This size is programmed in multiples
of four quadlets. The number of quadlets that have been received to the BIRX FIFO is available at register
130h. Only complete isochronous packets can be confirmed into the BIRX FIFO. If the storage space
available in the BIRX FIFO drops below 2 quadlets, then all incoming isochronous packets will not be
received. Partial packets that have accumulated in the BIRX at the time that storage space runs out are
purged from the FIFO.
The application has the option to receive only data to the BIRX (strip header/trailer) or to receive all data
to the BIRX (header /data/trailer.) The IRHS bit in register EC (AICR) controls this function.
The first packet in a queue of isochronous packets stored to the BIRX FIFO automatically have its header
and trailer quadlets stored to registers. The IRAV interrupt is generated to the application when this
operation completes.
There are four methods of receiving isochronous data to the BIRX FIFO. The control signals located in
register EC that necessary for these four modes are summarized in the following text. A detailed description
is also included for each mode.
MODE IRENABLE IRHS BDIRE
OUTPUT INTERFACE
PACKET FORMAT (RECEIVED
at BIRX)
1
1
1
1
Bulky Data Interface
Data only. Headers are stripped.
2
1
1
0
Microprocessor Interface Data only. Headers are stripped.
3
1
0
1
Bulky Data Interface
Header/Data/Trailer
4
1
0
0
Microprocessor Interface
Header/Data/Trailer
Mode 1: Receiving Isochronous Data to the Bulky Data Interface Using the BIRX,
Headers are Stripped
Data is received by the MPEG2Lynx, and the headers and trailer are automatically copied to registers 140h
and 144h, respectively. Only the data is received into the BIRX FIFO. The IRAV interrupt is signaled once
the headers have been copied and the data has been received to the BIRX FIFO. The BDOAVAIL signal
is activated once a full quadlet is in the FIFO (settings for register EC for this mode: IRENABLE=1, IRHS=1,
BDIRE=1) (see Figure 3–15).
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