TSB12LV41 Datasheet, PDF (23/195 Pages) Texas Instruments – IEEE 1394-1995 Link-Layer Controller for Consumer Applications

2.1 Bulky Data Interface
The bulky data interface (BDI) enables the TSB12LV41 to provide sustained data rates up to 160 Mbits/s.
The bulky data FIFO supports MPEG2 compressed DVB/DSS, asynchronous, and isochronous packets for
receive and transmit.
2.2 Bulky Data FIFO
The bulky data FIFO is where transmit and receive data is buffered via the bulky data interface (BDI). The
bulky data FIFO is partitioned into six logical FIFOs. Each logical FIFO size is programmable on four quadlet
boundaries. These six FIFOs are called:
• BDI MPEG2 (DVB)/DSS Transmit (BMDTX)
• BDI MPEG2 (DVB)/DSS Receive (BMDRX)
• BDI Asynchronous Transmit (BATX)
• BDI Asynchronous Receive (BARX)
• BDI Isochronous Transmit (BITX)
• BDI Isochronous Receive (BIRX)
The following sections give functional descriptions of these logical FIFOs.
2.2.1 BDI MPEG2 (DVB)/DSS Transmit FIFO (BMDTX)
The BMDTX FIFO is used to transmit either MPEG2 (DVB) or DSS data. Data is typically written to this FIFO
from the BDI or microcontroller in quadlets (four bytes). See the Bulky Data Interface section (Section 4)
for more detail on using this FIFO to transmit MPEG2 (DVB)/DSS data.
2.2.2 BDI MPEG2 (DVB)/DSS Receive FIFO (BMDRX)
The BMDRX FIFO is typically used to store MPEG2 (DVB)/DSS data received from the link-layer core to
be forwarded to a high-speed application via the BDI. Data can be written to this FIFO by either the link layer
core or the microcontroller. Note that only isochronous port 0 can access this FIFO. See the Bulky Data
Interface section (Section 4) for more details.
2.2.3 BDI Asynchronous Transmit FIFO (BATX)
The BATX FIFO is typically used to transmit asynchronous data packets from high-speed applications. Data
can be loaded into this FIFO with the BDI or the microcontroller.
2.2.4 BDI Asynchronous Receive FIFO (BARX)
The BARX FIFO is typically used to store received asynchronous data packets to be forwarded to a
high-speed application via the BDI. Data is provided to the BDI or the microcontroller interface. This FIFO
is also the default location for storing incoming Self-ID packets.
2.2.5 BDI Isochronous Transmit FIFO (BITX)
The BITX FIFO is typically used to transmit isochronous data packets from high-speed applications. Data
can be loaded into this FIFO with the BDI or the microcontroller.
2.2.6 BDI Isochronous Receive FIFO (BIRX)
The BIRX FIFO is typically used for receiving isochronous data and forwarding it to a high-speed application.
Data is provided to the BDI or microcontroller interface. Isochronous Ports 1 through 7 have access to this
FIFO. Each port can be programmed to filter incoming packets according to the Isochronous channel and/or
the isochronous header tag value.
2.3 MPEG2 (DVB)/DSS Transmit and Receive Control
The following sections give information on MPEG2 (DVB) and DSS transmit and receive control.
2.3.1 Local Time Register
This register is typically called the cycle timer. It contains the synchronized 1394 cycle timer as specified
by the IEEE 1394-1995 standard. The local time register is used to timestamp packets, which determines
2–3