TMS320LF2407 Datasheet, PDF (50/106 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2407, TMS320LF2406, TMS320LF2402
TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS
SPRS094C – APRIL 1999 – REVISED OCTOBER 1999
low-power modes
The ’240x has an IDLE instruction. When executed, the IDLE instruction stops the clocks to all circuits in the
CPU, but the clock output from the CPU continues to run. With this instruction, the CPU clocks can be shut down
to save power while the peripherals (clocked with CLKOUT) continue to run. The CPU exits the IDLE state if
it is reset, or, if it receives an interrupt request.
clock domains
All ’240x-based devices have two clock domains:
1. CPU clock domain – consists of the clock for most of the CPU logic
2. System clock domain – consists of the peripheral clock (which is derived from CLKOUT of the CPU) and
the clock for the interrupt logic in the CPU.
When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues
to run. This mode is also known as IDLE1 mode. The ’240x CPU also contains support for a second IDLE mode,
IDLE2. By asserting IDLE2 to the ’240x CPU, both the CPU clock domain and the system clock domain are
stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the
oscillator and WDCLK are also shut down when in IDLE2 mode.
Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the
IDLE instruction is executed (see Table 12). These bits are located in the System Control and Status
Register 1 (SCSR1), and they are described in the TMS320F243/’F241/’C242 DSP Controllers System and
Peripherals User’s Guide (literature number SPRU276).
Table 12. Low-Power Modes Summary
LOW-POWER MODE
CPU running normally
IDLE1 – (LPM0)
LPMx BITS
SCSR1
[13:12]
XX
00
CPU
CLOCK
DOMAIN
On
SYSTEM
CLOCK
DOMAIN
On
WDCLK
STATUS
On
PLL
STATUS
On
OSC
STATUS
On
Off
On
On
On
On
FLASH
POWER
EXIT
CONDITION
On
—
Peripheral
Interrupt,
On
External Interrupt,
Reset,
PDPINTA/B
IDLE2 – (LPM1)
Wakeup
Interrupts,
01
Off
Off
On
On
On
On
External Interrupt,
Reset,
PDPINTA/B
HALT – (LPM2)
[PLL/OSC power down]
1X
Off
Off
Off
Off
Off
Off
Reset,
PDPINTA/B
other power-down options
’240x devices have clock enable bits to the following on-chip peripherals: ADC, SCI, SPI, CAN, EVB, and EVA.
Clock to these peripherals are disabled after reset; thus, start-up power can be low for the device.
Depending on the application, these peripherals can be turned on/off to achieve low power.
Refer to the SCSR2 register for details on the peripheral clock enable bits.
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