TMS320LF2407 Datasheet, PDF (43/106 Pages) Texas Instruments – DSP CONTROLLERS

TMS320LF2407, TMS320LF2406, TMS320LF2402
TMS320LC2406, TMS320LC2404, TMS320LC2402
DSP CONTROLLERS
SPRS094C – APRIL 1999 – REVISED OCTOBER 1999
CAN memory map
Table 8 and Table 9 show the register and mailbox locations in the CAN module.
Table 8. Register Addresses^†
ADDRESS
OFFSET
NAME
DESCRIPTION
00h
MDER
Mailbox Direction/Enable Register (bits 7 to 0)
01h
TCR
Transmission Control Register (bits 15 to 0)
02h
RCR
Receive Control Register (bits 15 to 0)
03h
MCR
Master Control Register (bits 13 to 6, 1, 0)
04h
BCR2
Bit Configuration Register 2 (bits 7 to 0)
05h
BCR1
Bit Configuration Register 1 (bits 10 to 0)
06h
ESR
Error Status Register (bits 8 to 0)
07h
GSR
Global Status Register (bits 5 to 0)
08h
CEC
Transmit and Receive Error Counters (bits 15 to 0)
09h
CAN_IFR Interrupt Flag Register (bits 13 to 8, 6 to 0)
0Ah
CAN_IMR Interrupt Mask Register (bits 15, 13 to 0)
0Bh
LAM0_H Local Acceptance Mask Mailbox 0 and 1 (bits 31, 28 to 16)
0Ch
LAM0_L Local Acceptance Mask Mailbox 0 and 1 (bits 15 to 0)
0Dh
LAM1_H Local Acceptance Mask Mailbox 2 and 3 (bits 31, 28 to 16)
0Eh
LAM1_L Local Acceptance Mask Mailbox 2 and 3 (bits 15 to 0)
0Fh
Reserved Accesses assert the CAADDRx signal from the CAN peripheral (which asserts an Illegal Address error)
† _{All unimplemented register bits are read as zero, writes have no effect. Register bits are initialized to zero, unless otherwise stated in the definition.}
Table 9. Mailbox Addresses^‡
ADDRESS
OFFSET [5:0]
NAME
DESCRIPTION
UPPER HALF-WORD ADDRESS BIT 0 = 1
DESCRIPTION
LOWER HALF-WORD ADDRESS BIT 0 = 0
00h
MSGID0 Message ID for mailbox 0
Message ID for mailbox 0
02h
MSGCTRL0 Unused
RTR and DLC (bits 4 to 0)
Databyte 0, Databyte 1 (DBO = 1)
04h
Datalow0
Databyte 3, Databyte 2 (DBO = 0)
Databyte 2, Databyte 3 (DBO = 1)
Databyte 1, Databyte 0 (DBO = 0)
Databyte 4, Databyte 5 (DBO = 1)
06h
Datahigh0
Databyte 7, Databyte 6 (DBO = 0)
Databyte 6, Databyte 7 (DBO = 1)
Databyte 5, Databyte 4 (DBO = 0)
08h
MSGID1 Message ID for mailbox 1
Message ID for mailbox 1
0Ah
MSGCTRL1 Unused
RTR and DLC (bits 4 to 0)
Databyte 0, Databyte 1 (DBO = 1)
0Ch
Datalow1
Databyte 3, Databyte 2 (DBO = 0)
Databyte 2, Databyte 3 (DBO = 1)
Databyte 1, Databyte 0 (DBO = 0)
0Eh
Datahigh1 Databyte 4, Databyte 5 (DBO = 1)
Databyte 6, Databyte 7 (DBO = 1)
...
...
...
...
28h
MSGID5 Message ID for mailbox 5
Message ID for mailbox 5
2Ah
MSGCTRL5 Unused
RTR and DLC (bits 4 to 0)
Databyte 0, Databyte 1 (DBO = 1)
2Ch
Datalow5
Databyte 3, Databyte 2 (DBO = 0)
Databyte 2, Databyte 3 (DBO = 1)
Databyte 3, Databyte 2 (DBO = 0)
Databyte 4, Databyte 5 (DBO = 1)
2Eh
Datahigh5
Databyte 7, Databyte 6 (DBO = 0)
Databyte 6, Databyte 7 (DBO = 1)
Databyte 5, Databyte 4 (DBO = 0)
‡ _{The DBO (data byte order) bit is located in the MCR register and is used to define the order in which the data bytes are stored in the mailbox}
when received and the order in which the data bytes are transmitted. Byte 0 is the first byte in the message and Byte 7 is the last one shown
in the CAN message.
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
43