TMS28F033 Datasheet, PDF (50/52 Pages) Texas Instruments – 4194304-BIT SYNCHRONOUS FLASH MEMORY

CLK
A–1–A16 (word-
wide)
A0–A16
(double-word-wide)
E
WR
WE
LBA
BAA
OE
DQ0–DQ7 and
DQ24–DQ31
(word-wide)
DQ0–DQ31
(double-word-
wide)
ADVANCE INFORMATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A0
A1
A2
A3
00000h
D0
D1
D2
D3
One-Cycle CSM Command
QV
RY/BY
VPP
RP
BASIC/ENHANCED
PIN SET
DCR0
Basic pin set (DCR0 = 0)
Enhanced pin set (DCR0 = 1)
OE
MODE
DCR1
0
(see Note D)
0
(see Note D)
WE
MODE
DCR2
0
(see Note E)
0
(see Note E)
DIS/WORD
DCR3
Optional
Optional
LRV/BAA
DCR4
1
(see Note F)
1
(see Note F)
BURST
LENGTH
DCR25,24
X
X
BURST
LATENCY (X)
DCR29,28
Optional
(see Note G)
Optional
(see Note G)
BURST
LATENCY (Y)
DCR30
X
X
x16 WRITE
OPTION
DCR31
X
X
NOTES: A. X is a don’t care.
B. See Table 8 for DCR setting descriptions.
C. LBA (for A1) can go low as early as CLK2.
D. Synchronous and asynchronous OE are available (see Figure 20); DCR1 = 0 and DCR1 = 1, respectively.
E. Synchronous WE is required to perform overlapping writes.
F. For single reads, the number of wait states can be set by selecting BAA usage (DCR4 = 1) and by setting DCR[29:28] = (number of wait states). BAA usage is
not required to perform single reads.
G. In the timing diagram above, both 1 wait state (CLK 1 to CLK 2) and 2 wait states (CLK 3 to CLK 5) are shown, corresponding to DCR[29:28] = 01 and 10,
respectively. OE can be used to control the number of wait states for single reads by setting DCR[29:28] = 00.
Figure 27. Overlapping Read/Write Cycles With Device Configuration Register Settings