TMS28F033 Datasheet, PDF (15/52 Pages) Texas Instruments – 4194304-BIT SYNCHRONOUS FLASH MEMORY

burst access and burst performance (continued)
TMS28F033
4 194 304-BIT
SYNCHRONOUS FLASH MEMORY
SMJS833 – NOVEMBER 1997
Table 11. Burst Performance (Clock Cycles to Read)
FREQUENCY (MHz)
< 25 (see Note 9)
x16 Mode
LINEAR†
A–1 = 0
4–2– . . . –2
A–1 = 1
4–2– . . . –2
INTERLEAVE
4–2– . . . –2
x32 Mode
LINEAR
4–2– . . . –2
< 33 (see Note 9)
4–2– . . . –2
5–1– . . . –1
4–1– . . . –1
4–2– . . . –2
< 40 (see Notes 9 and 10)
—
—
—
5–2– . . . –2
† _{The state of A–1 when the address is latched (at CLK 1 in Figure 14)}
NOTES: 9. The Y-latency notation for MOD4 has three 1s/2s (–1–1–1/–2–2–2). For MOD8, there are seven 1s/2s
(–1–1–1–1–1–1–1/–2–2–2–2–2–2–2). MOD16 has fifteen 1’s/2’s, and MOD32 has 31 1’s/2’s.
10. To obtain 5–2– . . . –2 (40 MHz), the required DCR settings are 4–2– . . . –2, and asynchronous OE with BAA-controlled burst.
burst suspend/resume
Burst suspension is the ability to hold the address advance and the data on the output I/Os DQ0 – DQ7 and
DQ24– DQ31 if in x16 mode, or on DQ0 – DQ31 if in x32 mode. For DCR4 = 1, the suspension of a burst
sequence is possible by bringing BAA high. To resume the burst, bring BAA low again (see Figure 18). When
DCR4 = 0, the suspension of the burst is possible by bringing OE high. To resume the burst, bring OE low again.
linear burst order (LBO)
When performing a burst read, a single starting address is entered into the device and then the TMS28F033
internally accesses a sequence of locations based on that starting address. The burst sequence is determined
by the linear burst order (LBO) setting (see the Terminal Functions table). When LBO = V_IL, the burst order is
linear 0–1–2–3 . . . .; and when LBO = V_IH, the burst order is interleave (see Table 12). Linear burst order is
available with MOD4, MOD8, MOD16, and MOD32. Interleave burst order is available only with MOD4, and only
with the 16-bit data bus.
Table 12. 2-Bit Linear and Interleaved-Burst Sequences (MOD4)
BURST
SEQUENCE
START
ADDRESS
A1 – A0 For x32 Mode, AND A0 – A–1 For x16 Mode
DECIMAL
2ND
3RD
4TH†
START
BINARY
2ND
3RD
4TH†
0
1
2
3
00
01
10
11
Linear
1
2
3
0
01
10
11
00
(see Note 11)
2
3
0
1
01
10
11
00
3
0
1
2
11
00
01
10
0
1
2
3
00
01
10
11
Interleave
1
0
3
2
01
00
11
10
(see Note 12)
2
3
0
1
10
11
00
01
3
2
1
0
11
10
01
00
† _{Burst sequence continues until OE or BAA is brought high.}
NOTES: 11. Linear burst is available with both x16 and x32 for MOD4, MOD8, MOD16, and MOD32. For linear burst set LBO=VIL.
12. Interleaved burst is available only with MOD4, and only with the 16-bit data bus. For interleave burst set LBO =VIH.
word (X16) write option
DCR31 determines the number of write cycles for word-wide programming. For DCR31 = 0, the device performs
two-cycle writes, or with DCR31 = 1, the device performs three-cycle writes (see Table 5). See Figure 22 and
Figure 24 for synchronous two- and three-cycle writes, respectively. For asynchronous two-cycle writes, see
Figure 23.
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