ADS62P19 Datasheet, PDF (50/65 Pages) Texas Instruments – Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs

ADS62P19
SLAS937 – APRIL 2013
www.ti.com
0.1mF
Differential Sine-wave
Clock Input
R_T
0.1mF
CLKP
CLKM
Z_o
Typical LVDS
Clock Input
Z_o
0.1mF
100W
0.1mF
CLKP
CLKM
R_T = termination resistor if necessary
Figure 53. Differential Sine-Wave Clock Driving
Circuit
Figure 54. Typical LVDS Clock Driving Circuit
Typical LVPECL
Clock Input
Z_o
0.1mF
150W
Z_o
150W
100W
0.1mF
CLKP
CLKM
0.1mF
CMOS Clock Input
0.1mF
CLKP
VCM
CLKM
Figure 55. Typical LVPECL Clock Driving Circuit Figure 56. Typical LVCMOS Clock Driving Circuit
GAIN PROGRAMMABILITY
The ADS62P19 includes gain settings that can be used to obtain improved SFDR performance (compared to no
gain). Gain is programmable from 0 dB to 6 dB (in 0.5-dB steps). For each gain setting, the analog input full-
scale range scales proportionally, as shown in Table 31. SFDR improvement is achieved at the expense of SNR;
for each 1-dB gain step, SNR degrades by approximately 1 dB. SNR degradation is reduced at high input
frequencies. As a result, gain is very useful at high input frequencies because SFDR improvement is significant
with marginal degradation in SNR. Therefore, gain can be used to trade-off between SFDR and SNR. Note that
the default gain after reset is 0 dB.
GAIN (dB)
0
1
2
3
4
5
6
Table 31. Full-Scale Range Across Gains
DESCRIPTION
Default after reset
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
Fine, programmable
FULL-SCALE (V_PP)
2
1.78
1.59
1.42
1.26
1.12
1.00
50
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