ADS62P19 Datasheet, PDF (45/65 Pages) Texas Instruments – Dual-Channel, 11-Bit, 250-MSPS ADC With DDR LVDS and Parallel CMOS Outputs

ADS62P19
www.ti.com
SLAS937 – APRIL 2013
Drive Circuit Requirements
For optimum performance, the analog inputs must be driven differentially. This configuration improves the
common-mode noise immunity and even-order harmonic rejection. A 5-Ω to 15-Ω resistor in series with each
input pin is recommended to damp out ringing caused by package parasitic.
SFDR performance can be limited because of several reasons: the effect of sampling glitches (as described in
this section), nonlinearity of the sampling circuit, and nonlinearity of the quantizer that follows the sampling
circuit. Depending on the input frequency, sample rate, and input amplitude, one of these restrictions plays a
dominant part in limiting performance.
At very high input frequencies (greater than approximately 300 MHz), SFDR is determined largely by the device
sampling circuit nonlinearity. At low input amplitudes, the quantizer nonlinearity usually limits performance.
Glitches are caused by the opening and closing of the sampling switches. The driving circuit should present a
low source impedance to absorb these glitches. Otherwise, these glitches might limit performance, mainly at low
input frequencies (up to approximately 200 MHz). Low impedance (less than 50 Ω) must also be presented for
the common-mode switching currents. This impedance can be achieved by using two resistors from each input
terminated to the common-mode voltage (VCM).
The device includes an internal R-C filter from each input to ground. The purpose of this filter is to absorb the
sampling glitches inside the device itself. The cutoff frequency of the R-C filter involves a trade-off. A lower cutoff
frequency (larger C) absorbs glitches better, but reduces the input bandwidth. On the other hand, with a higher
cutoff frequency (smaller C), bandwidth support is maximized. However, the sampling glitches must be supplied
by the external drive circuit. This configuration has limitations because of the presence of the package bond-wire
inductance.
In the ADS62P19, the R-C component values have been optimized while supporting high input bandwidth (up to
700 MHz). However, in applications with input frequencies up to 200 MHZ to 300 MHz, the filtering of the glitches
can be improved further using an external R-C-R filter (see Figure 47 and Figure 48).
In addition, the drive circuit may have to be designed to provide a low insertion loss over the desired frequency
range and matched impedance to the source. During this process, ADC input impedance must be considered.
Figure 45 and Figure 46 show the impedance (Z_IN = R_IN || C_IN) at the ADC input pins.
100
4.5
10
4.0
3.5
1
3.0
2.5
0.10
2.0
0.01
0
100 200 300 400 500 600 700 800 900 1000
f - Frequency - MHz
Figure 45. ADC Analog Input Resistance (R_IN)
Across Frequency
1.5
1.0
0
100 200 300 400 500 600 700 800 900 1000
f − Frequency − MHz
G075
Figure 46. ADC Analog Input Capacitance (C_IN)
Across Frequency
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