TPA5050_07 Datasheet, PDF (5/21 Pages) Texas Instruments – STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL

TPA5050
www.ti.com
SLOS492B – MAY 2006 – REVISED MAY 2007
Serial Audio Input Ports
over recommended operating conditions (unless otherwise noted)
PARAMETER
f_SCLKIN Frequency, BCLK 32 × fs, 48 × fs, 64 × fs
t_su1 Setup time, LRCLK to BCLK rising edge
t_h1
Hold time, LRCLK from BCLK rising edge
t_su2 Setup time, DATA to BCLK rising edge
t_h2
Hold time, DATA from BCLK rising edge
LRCLK frequency
BCLK duty cycle
LRCLK duty cycle
BCLK rising edges between LRCLK rising edges
TEST CONDITIONS
MIN
1.024
10
10
10
10
32
LRCLK duty cycle = 50%
32
TYP
48
50%
50%
MAX
12.288
192
UNIT
MHz
ns
ns
ns
ns
kHz
64 BCLK edges
BCLK
(Input)
LRCLK
(Input)
th1
tsu1
th2
tsu2
DATA
Figure 3. Serial Data Interface Timing
APPLICATION INFORMATION
AUDIO SERIAL INTERFACE
The audio serial interface for the TPA5050 consists of a 3-wire synchronous serial port. It includes LRCLK,
BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA into
the serial shift register of the audio interface. Serial data is clocked into the TPA5050 on the rising edge of
BCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers of
the serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64
times the sampling frequency for right-justified, left-justified, and I²S formats. A system clock is not necessary for
the operation of the TPA5050.
AUDIO DATA FORMATS AND TIMING
The TPA5050 supports industry-standard audio data formats, including right-justified, I²S, and left-justified. The
data formats are shown in Figure 4. Data formats are selected using the I²C interface and register map (see
Table 1).
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