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| TLC5615C_07 Datasheet, PDF (5/21 Pages) Texas Instruments – 10-BIT DIGITAL-TO-ANALOG CONVERTERS | |||
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TLC5615C, TLC5615I
www.ti.com
SLAS142E â OCTOBER 1996 â REVISED JUNE 2007
OPERATING CHARACTERISTICS
over recommended operating free-air temperature range, VDD = 5V ±5%, Vref = 2.048V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
ANALOG OUTPUT DYNAMIC PERFORMANCE
SR
Output slew rate
ts
Output settling time
Glitch energy
CL = 100pF,
TA= +25°C
To 0.5LSB,
RL = 10kâ¦,
DIN = All 0s to all 1s
RL = 10kâ¦,
CL = 100pF, (1)
0.3 0.5
12.5
5
REFERENCE INPUT (REFIN)
Reference feedthrough
REFIN = 1VPP at 1kHz + 2.048Vdc (2)
â80
Reference input
bandwidth (fâ3dB)
REFIN = 0.2VPP + 2.048Vdc
30
UNIT
V/µs
µs
nV-s
dB
kHz
(1) Settling time is the time for the output signal to remain within ±0.5LSB of the final measured value for a digital input code change of 000
hex to 3FF hex or 3FF hex to 000 hex.
(2) Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref input = 2.048Vdc + 1Vpp at 1kHz.
PARAMETER MEASUREMENT INFORMATION
CS
th(CSH0)
ÃÃÃÃÃÃÃÃÃ SCLK
ÃÃÃ See Note A
ÃÃÃÃÃ tsu(DS)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ DIN
tsu(CSS)
tw(CH)
th(DH)
tw(CL)
ÃÃÃÃ th(CSH1)
tw(CS)
tsu(CS1)
ÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃÃ SeeNoteC SeeNoteA
tpd(DOUT)
DOUT
Previous LSB
See Note B
MSB
LSB
NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.
B. Data input from preceeding conversion cycle.
C. Sixteenth SCLK falling edge
Figure 1. Timing Diagram
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