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TLC5615C_07 Datasheet, PDF (4/21 Pages) Texas Instruments – 10-BIT DIGITAL-TO-ANALOG CONVERTERS
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TLC5615C, TLC5615I
SLAS142E – OCTOBER 1996 – REVISED JUNE 2007
VOLTAGE OUTPUT (OUT)
PARAMETER
TEST CONDITIONS
VO
Voltage output range
Output load regulation accuracy
IOSC
Output short circuit current
VOL(low) Output voltage, low-level
VOH(high) Output voltage, high-level
REFERENCE INPUT (REFIN)
RL= 10kΩ
VO(OUT) = 2V,
OUT to VDD or AGND
IO(OUT)≤ 5mA
IO(OUT)≤– 5mA
RL = 2kΩ
VI
Input voltage
ri
Input resistance
Ci
Input capacitance
DIGITAL INPUTS (DIN, SCLK, CS)
VIH
High-level digital input voltage
VIL
Low-level digital input voltage
IIH
High-level digital input current
IIL
Low-level digital input current
Ci
Input capacitance
DIGITAL OUTPUT (DOUT)
VI = VDD
VI = 0
VOH
Output voltage, high-level
VOL
Output voltage, low-level
POWER SUPPLY
IO = –2mA
IO = 2mA
VDD
Supply voltage
IDD
Power supply current
VDD = 5.5V, No load,
All inputs = 0V or VDD
VDD= 5.5V, No load,
All inputs = 0V or VDD
ANALOG OUTPUT DYNAMIC PERFORMANCE
Vref = 0
Vref = 2.048V
Signal-to-noise + distortion, S/(N+D)
Vref = 1VPP at 1kHz + 2.048Vdc,
code = 11 1111 1111(1)
(1) The limiting frequency value at 1VPP is determined by the output-amplifier slew rate.
DIGITAL INPUT TIMING REQUIREMENTS (See Figure 1)
tsu(DS)
th(DH)
tsu(CSS)
tsu(CS1)
th(CSH0)
th(CSH1)
tw(CS)
tw(CL)
tw(CH)
PARAMETER
Setup time, DIN before SCLK high
Hold time, DIN valid after SCLK high
Setup time, CS low to SCLK high
Setup time, CS high to SCLK high
Hold time, SCLK low to CS low
Hold time, SCLK low to CS high
Pulse duration, minimum chip select pulse width high
Pulse duration, SCLK low
Pulse duration, SCLK high
OUTPUT SWITCHING CHARACTERISTICS
tpd(DOUT)
PARAMETER
Propagation delay time, DOUT
CL = 50pF
TEST CONDITIONS
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MIN TYP
MAX UNIT
0
VDD–0.4
V
0.5 LSB
20
mA
0.25
V
4.75
V
0
VDD–2
V
10
MΩ
5
pF
2.4
8
V
0.8
V
±1 µA
±1 µA
pF
VDD–1
V
0.4
V
4.5
5
150
230
5.5
V
250 µA
350 µA
60
dB
MIN NOM MAX UNIT
45
ns
0
ns
1
ns
50
ns
1
ns
0
ns
20
ns
25
ns
25
ns
MIN NOM MAX UNIT
50 ns
4
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