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THS6214 Datasheet, PDF (5/41 Pages) Texas Instruments – Dual-Port, Differential, VDSL2 Line Driver Amplifiers
THS6214
www.ti.com ....................................................................................................................................................................................................... SBOS431 – MAY 2009
ELECTRICAL CHARACTERISTICS: VS = ±12V (continued)
At TA = +25°C, GDIFF = +10V/V with RL = 100Ω differential load, RADJ = 0Ω, active impedance circuit configuration, and full
bias, unless otherwise noted. Each port is independently tested. Boldface values are 100% tested at +25°C.
PARAMETER
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Noninverting input resistance
Inverting input resistance
OUTPUT CHARACTERISTICS(2)
Output voltage swing
Output current (sourcing and sinking)
Short-circuit output current
Output impedance
Crosstalk
POWER SUPPLY
Operating voltage
IS+ Quiescent current
IS– Quiescent current
Current through GND pin
Power-supply rejection ratio
(+PSRR)
Power-supply rejection ratio
(–PSRR)
CONDITIONS
Each input
TA = –40°C to +85°C
Each input
TA = –40°C to +85°C
RL = 100Ω, each output
RL = 50Ω, each output
TA = –40°C to +85°C
RL = 25Ω, each output
TA = –40°C to +85°C
RL = 25Ω, based on VOUT tests
TA = –40°C to +85°C
f = 1MHz, differential
f = 1MHz, VOUT = 2VPP, Port 1 to Port 2
TA = –40°C to +85°C
Per port, full bias (Bias-1 = 0, Bias-2 = 0)
TA = –40°C to +85°C
Per port, mid bias (Bias-1 = 1, Bias-2 = 0)
TA = –40°C to +85°C
Per port, low bias (Bias-1 = 0, Bias-2 = 1)
TA = –40°C to +85°C
Per port, bias off (Bias-1 = 1, Bias-2 = 1)
TA = –40°C to +85°C
Per port, full bias (Bias-1 = 0, Bias-2 = 0)
TA = –40°C to +85°C
Per port, mid bias (Bias-1 = 1, Bias-2 = 0)
TA = –40°C to +85°C
Per port, low bias (Bias-1 = 0, Bias-2 = 1)
TA = –40°C to +85°C
Per port, bias off (Bias-1 = 1, Bias-2 = 1)
TA = –40°C to +85°C
Per port, full bias (Bias-1 = 0, Bias-2 = 0)
Differential
TA = –40°C to +85°C
Differential
TA = –40°C to +85°C
THS6214IRHF, IPWP
MIN
TYP
MAX
±9
±9.5
±8.6
53
65
49
500 || 2
50
±10.6
±10.4
±10.2
±10
±408
±400
±10.9
±10.8
±10.4
±416
1
0.2
–90
±5
±12
±14
±5
±14
19.5
21
22.5
17
24
15
16.2
17.4
12.8
18.6
10
11.2
12.4
8.1
13.2
0.4
0.8
1
18.5
20
21.5
16
23
14
15.2
16.4
11.8
17.6
9
10.2
11.6
7.1
11.4
0.1
0.3
0.8
1
54
66
52
52
65
50
UNIT
TEST
LEVEL (1)
V
A
V
B
dB
A
dB
B
kΩ || pF
C
Ω
C
V
C
V
A
V
B
V
A
V
B
mA
A
mA
B
A
C
Ω
C
dB
C
V
A
V
C
mA
A
mA
B
mA
A
mA
B
mA
A
mA
B
mA
A
mA
B
mA
A
mA
B
mA
A
mA
B
mA
A
mA
B
mA
A
mA
B
mA
C
dB
A
dB
B
dB
A
dB
B
(2) Test circuit is shown in Figure 1.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): THS6214
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