TAS5012_15 Datasheet, PDF (5/18 Pages) Texas Instruments – TRUE DIGITAL AUDIO AMPLIFIER TAS 5012 DIGITAL AUDIO PWM PROCESSOR

TAS5012
SLES006A − SEPTEMBER 2001 − REVISED DECEMBER 2001
functional description
serial audio port
The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and
a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 32 kHz, 44.1 kHz, 48 kHz,
88.2 kHz, 96 kHz, 176.4 kHz, or 192 kHz) stereo. See the serial interface formats section.
system clocks—master mode and slave mode
The TAS5012 allows multiple system clocking schemes. In this document, master mode indicates that the TAS5012
provides system clocks to other parts of the system (M_S=1). Audio system clocks of frequency 256 Fs MCLK_OUT,
64 Fs SCLK, and Fs LRCLK are output from this device when it is configured in master mode. Slave mode indicates
that a system master other than the TAS5012 provides system clocks (LRCLK, SCLK, and MCLK_IN) to the TAS5012
(M_S = 0). The TAS5012 operates with LRCLK and SCLK synchronized to MCLK. TAS5012 does not require any
specific phase relationship between LRCLK and MCLK, but there must be synchronization. In the slave mode
MCLK_OUT is driven low. Table 1 shows all the possible master and slave modes. When operating in quad mode
(Fs = 176.4 kHz or 192 kHz), the device works in slave mode only with MCLK_IN = 128 Fs.
oscillator/sampling frequency
The sampling frequency is determined by the crystal (master mode) or master clock in (slave mode) which should
be either 8.192 MHz (Fs = 32 kHz), 11.2896 MHz (Fs = 44.1 kHz), or 12.288 MHz (Fs = 48 kHz). Twice the
normal sampling frequency can be selected by using the DBSPD pin which allows usage of Fs = 88.2 kHz or Fs
= 96 kHz. In the double-speed slave mode (DBSPD = 1, M_S = 0), the external clock input is either 22.5796 MHz
(Fs = 88.2 kHz) or 24.576 MHz (Fs = 96 kHz). Note that 32-kHz sampling is supported in the normal speed
modes. Table 1 explains the proper clock selection.
Table 1. Oscillator, External Clock, and PLL Functions
DESCRIPTION
M_S DBSPD
XTL_IN
(MHz)^†
MCLK_IN
(MHz)^‡
Master, normal speed
1
0
8.192
—
Master, normal speed
1
0
11.2896
—
Master, normal speed
Master, double speed
Master, double speed
Slave, normal speed
Slave, normal speed
Slave, normal speed
Slave, double speed
Slave, double speed
1
0
12.288
—
1
1
—
22.5792§
1
1
—
24.576§
0
0
—
8.192§
0
0
—
11.2896§
0
0
—
12.288§
0
1
—
22.5792§
0
1
—
24.576§
Slave, quad speed||
0
0
—
22.5792§
Slave, quad speed||
0
0
—
24.576§
† _{Either a crystal oscillator or an external clock of the specified frequency can be connected to XTL_IN.}
‡ _{MCLK_IN tied low when input to XTL_IN is provided; XTL_IN tied low when MCLK_IN is provided.}
§ _{External MCLK connected to MCLK_IN input}
¶ _{SCLK and LRCLK are outputs when M_S = 1, inputs when M_S = 0.}
# _{MCLK_OUT is driven low when M_S = 0.}
|| _{Quad speed mode is detected automatically. when DBSPD = 0.}
SCLK LRCLK
(MHz)^¶ (kHz)^¶
2.048
32
2.8224 44.1
3.072
48
5.6448 88.2
6.144
96
2.048
32
2.8224 44.1
3.072
48
5.6448 88.2
6.144
96
11.2896 176.4
12.288
192
MCLK_OUT
(MHz)^#
8.192
11.2896
12.288
22.5792
24.576
Digital GND
Digital GND
Digital GND
Digital GND
Digital GND
Digital GND
Digital GND
phase-locked loop (PLL)/clock generation
A low jitter PLL is incorporated for internal use. Connections for the PLL external loop filter are provided as
PLL_FLT_RET and PLL_FLT_OUT. If the PLL loses lock, the PWM output status pins (VALID_L and VALID_R) go
low. Note that VALID_L and VALID_R can go low for other conditions as well. See the error status reporting section.
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