TAS5012_15 Datasheet, PDF (14/18 Pages) Texas Instruments – TRUE DIGITAL AUDIO AMPLIFIER TAS 5012 DIGITAL AUDIO PWM PROCESSOR

TAS5012
SLES006A − SEPTEMBER 2001 − REVISED DECEMBER 2001
PARAMETER MEASUREMENT INFORMATION
SCLK
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _SDIN
tsu(SDIN)
th(SDIN)
Figure 11. Right-Justified, IIS, Left-Justified Serial Protocol Timing
SCLK
tsu(LRCLK)
LRCLK
NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns)
Figure 12. Right, Left, and IIS Serial Mode Timing Requirement
SCLK
LRCLK
(Output)
MCLK
(Output)
t(MSD)
t(MLRD)
Figure 13. Serial Audio Ports Master Mode Timing
SCLK
LRCLK
tsu(LRCLK)
th(LRCLK)
tw(FSHIGH)
tsu(SDIN)
SDIN ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 14. DSP Serial Port Timing
th(SDIN)
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