SN54AC574 Datasheet, PDF (5/16 Pages) Texas Instruments – OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

From Output
Under Test
CL = 50 pF
(see Note A)
SN54AC574, SN74AC574
OCTAL DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS
WITH 3ĆSTATE OUTPUTS
SCAS541E − OCTOBER 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
500 Ω
500 Ω
2 × VCC
S1
Open
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 × VCC
Open
LOAD CIRCUIT
tw
Input ^{50% VCC}
3V
50% VCC
0V
VOLTAGE WAVEFORMS
Timing Input
tsu
Data Input
50% VCC
th
50% VCC
50% VCC
VOLTAGE WAVEFORMS
VCC
0V
VCC
0V
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
50% VCC
50% VCC
VCC
0V
50% VCC
tPHL
VOH
50% VCC
VOL
50% VCC
tPLH
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZL
tPZH
50% VCC
50% VCC
VCC
0V
50%VCC
tPLZ
≈VCC
VOL + 0.3 V _VOL
tPHZ
50% VCC
VOH − 0.3 V ^VOH
≈0 V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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